Merge "drm/msm/sde: interface TE interrupt implementation" (d89244a4) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/msm/sde/sde_hw_interrupts.c

+124 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,11 @@
		#define MDP_AD4_INTR_EN_OFF 0x41c
		#define MDP_AD4_INTR_CLEAR_OFF 0x424
		#define MDP_AD4_INTR_STATUS_OFF 0x420
		#define MDP_INTF_TEAR_INTF_1_IRQ_OFF 0x6E800
		#define MDP_INTF_TEAR_INTF_2_IRQ_OFF 0x6E900
		#define MDP_INTF_TEAR_INTR_EN_OFF 0x0
		#define MDP_INTF_TEAR_INTR_STATUS_OFF 0x4
		#define MDP_INTF_TEAR_INTR_CLEAR_OFF 0x8

		/**
		* WB interrupt status bit definitions
		@@ -177,6 +182,16 @@
		#define SDE_INTR_STREN_OUTROI_UPDATED BIT(2)
		#define SDE_INTR_STREN_INROI_UPDATED BIT(1)
		#define SDE_INTR_BACKLIGHT_UPDATED BIT(0)

		/**
		* INTF Tear IRQ register bit definitions
		*/
		#define SDE_INTR_INTF_TEAR_AUTOREFRESH_DONE BIT(0)
		#define SDE_INTR_INTF_TEAR_WR_PTR BIT(1)
		#define SDE_INTR_INTF_TEAR_RD_PTR BIT(2)
		#define SDE_INTR_INTF_TEAR_TE_DETECTED BIT(3)
		#define SDE_INTR_INTF_TEAR_TEAR_DETECTED BIT(4)

		/**
		* struct sde_intr_reg - array of SDE register sets
		* @clr_off: offset to CLEAR reg
		@@ -256,6 +271,16 @@ static const struct sde_intr_reg sde_intr_set[] = {
		MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF,
		MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF,
		MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF,
		},
		{
		MDP_INTF_TEAR_INTF_1_IRQ_OFF + MDP_INTF_TEAR_INTR_CLEAR_OFF,
		MDP_INTF_TEAR_INTF_1_IRQ_OFF + MDP_INTF_TEAR_INTR_EN_OFF,
		MDP_INTF_TEAR_INTF_1_IRQ_OFF + MDP_INTF_TEAR_INTR_STATUS_OFF,
		},
		{
		MDP_INTF_TEAR_INTF_2_IRQ_OFF + MDP_INTF_TEAR_INTR_CLEAR_OFF,
		MDP_INTF_TEAR_INTF_2_IRQ_OFF + MDP_INTF_TEAR_INTR_EN_OFF,
		MDP_INTF_TEAR_INTF_2_IRQ_OFF + MDP_INTF_TEAR_INTR_STATUS_OFF,
		}
		};

		@@ -767,6 +792,105 @@ static const struct sde_irq_type sde_irq_map[] = {
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

		/* BEGIN MAP_RANGE: 320-351 INTF_1_TEAR INTR */
		/* irq_idx: 320-322 */
		{ SDE_IRQ_TYPE_INTF_TEAR_AUTO_REF, INTF_1,
		SDE_INTR_INTF_TEAR_AUTOREFRESH_DONE, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_WR_PTR, INTF_1,
		SDE_INTR_INTF_TEAR_WR_PTR, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_RD_PTR, INTF_1,
		SDE_INTR_INTF_TEAR_RD_PTR, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK, INTF_1,
		SDE_INTR_INTF_TEAR_TE_DETECTED, 10},
		/* irq_idx: 323 */
		{ SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK, INTF_1,
		SDE_INTR_INTF_TEAR_TEAR_DETECTED, 10},
		/* irq_idx: 324-327 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		/* irq_idx: 328-331 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		/* irq_idx: 332-335 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		/* irq_idx: 336-339 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		/* irq_idx: 340-343 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		/* irq_idx: 344-347 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		/* irq_idx: 348-351 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 10},

		/* BEGIN MAP_RANGE: 352-383 INTF_2_TEAR INTR */
		/* irq_idx: 352-354 */
		{ SDE_IRQ_TYPE_INTF_TEAR_AUTO_REF, INTF_2,
		SDE_INTR_INTF_TEAR_AUTOREFRESH_DONE, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_WR_PTR, INTF_2,
		SDE_INTR_INTF_TEAR_WR_PTR, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_RD_PTR, INTF_2,
		SDE_INTR_INTF_TEAR_RD_PTR, 10},
		{ SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK, INTF_2,
		SDE_INTR_INTF_TEAR_TE_DETECTED, 10},
		/* irq_idx: 355 */
		{ SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK, INTF_2,
		SDE_INTR_INTF_TEAR_TEAR_DETECTED, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		/* irq_idx: 356-359 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		/* irq_idx: 360-363 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		/* irq_idx: 364-367 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		/* irq_idx: 368-371 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		/* irq_idx: 372-375 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		/* irq_idx: 376-379 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		/* irq_idx: 380-383 */
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		{ SDE_IRQ_TYPE_RESERVED, 0, 0, 11},
		};

		static int sde_hw_intr_irqidx_lookup(enum sde_intr_type intr_type,

drivers/gpu/drm/msm/sde/sde_hw_interrupts.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,11 @@
		* @SDE_IRQ_TYPE_PROG_LINE: Programmable Line interrupt
		* @SDE_IRQ_TYPE_AD4_BL_DONE: AD4 backlight
		* @SDE_IRQ_TYPE_CTL_START: Control start
		* @SDE_IRQ_TYPE_INTF_TEAR_RD_PTR: INTF Tear read pointer
		* @SDE_IRQ_TYPE_INTF_TEAR_WR_PTR: INTF Tear write pointer
		* @SDE_IRQ_TYPE_INTF_TEAR_AUTO_REF: INTF Tear auto refresh
		* @SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK: INTF Tear Tear check
		* @SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK: INTF Tear TE detection
		* @SDE_IRQ_TYPE_RESERVED: Reserved for expansion
		*/
		enum sde_intr_type {
		@@ -86,6 +91,11 @@ enum sde_intr_type {
		SDE_IRQ_TYPE_PROG_LINE,
		SDE_IRQ_TYPE_AD4_BL_DONE,
		SDE_IRQ_TYPE_CTL_START,
		SDE_IRQ_TYPE_INTF_TEAR_RD_PTR,
		SDE_IRQ_TYPE_INTF_TEAR_WR_PTR,
		SDE_IRQ_TYPE_INTF_TEAR_AUTO_REF,
		SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK,
		SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK,
		SDE_IRQ_TYPE_RESERVED,
		};