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Commit d865110c authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915: merge get_gtt_alignment/get_unfenced_gtt_alignment() 



The two functions are rather similar, so merge them.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent af5163ac

drivers/gpu/drm/i915/i915_drv.h

+2 −3
Original line number Original line Diff line number Diff line
@@ -1565,9 +1565,8 @@ void i915_gem_free_all_phys_object(struct drm_device *dev); 
void i915_gem_release(struct drm_device *dev, struct drm_file *file);

void i915_gem_release(struct drm_device *dev, struct drm_file *file);





uint32_t

uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,

i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,

				    uint32_t size,

			    int tiling_mode, bool fenced);

				    int tiling_mode);





int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,

int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,

				    enum i915_cache_level cache_level);

				    enum i915_cache_level cache_level);

drivers/gpu/drm/i915/i915_gem.c

+7 −37
Original line number Original line Diff line number Diff line
@@ -1463,16 +1463,15 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) 
 * Return the required GTT alignment for an object, taking into account

 * Return the required GTT alignment for an object, taking into account

 * potential fence register mapping.

 * potential fence register mapping.

 */

 */

static uint32_t

uint32_t

i915_gem_get_gtt_alignment(struct drm_device *dev,

i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,

			   uint32_t size,

			   int tiling_mode, bool fenced)

			   int tiling_mode)

{

{

	/*

	/*

	 * Minimum alignment is 4k (GTT page size), but might be greater

	 * Minimum alignment is 4k (GTT page size), but might be greater

	 * if a fence register is needed for the object.

	 * if a fence register is needed for the object.

	 */

	 */

	if (INTEL_INFO(dev)->gen >= 4 ||

	if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||

	    tiling_mode == I915_TILING_NONE)

	    tiling_mode == I915_TILING_NONE)

		return 4096;

		return 4096;
@@ -1483,35 +1482,6 @@ i915_gem_get_gtt_alignment(struct drm_device *dev, 
	return i915_gem_get_gtt_size(dev, size, tiling_mode);

	return i915_gem_get_gtt_size(dev, size, tiling_mode);

}

}





/**

 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an

 *					 unfenced object

 * @dev: the device

 * @size: size of the object

 * @tiling_mode: tiling mode of the object

 *

 * Return the required GTT alignment for an object, only taking into account

 * unfenced tiled surface requirements.

 */

uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,

				    uint32_t size,

				    int tiling_mode)

{

	/*

	 * Minimum alignment is 4k (GTT page size) for sane hw.

	 */

	if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||

	    tiling_mode == I915_TILING_NONE)

		return 4096;



	/* Previous hardware however needs to be aligned to a power-of-two

	 * tile height. The simplest method for determining this is to reuse

	 * the power-of-tile object size.

	 */

	return i915_gem_get_gtt_size(dev, size, tiling_mode);

}



static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)

static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)

{

{

	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;

	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
@@ -2934,11 +2904,11 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, 
					   obj->tiling_mode);

					   obj->tiling_mode);

	fence_alignment = i915_gem_get_gtt_alignment(dev,

	fence_alignment = i915_gem_get_gtt_alignment(dev,

						     obj->base.size,

						     obj->base.size,

						     obj->tiling_mode);

						     obj->tiling_mode, true);

	unfenced_alignment =

	unfenced_alignment =

		i915_gem_get_unfenced_gtt_alignment(dev,

		i915_gem_get_gtt_alignment(dev,

						    obj->base.size,

						    obj->base.size,

						    obj->tiling_mode);

						    obj->tiling_mode, false);





	if (alignment == 0)

	if (alignment == 0)

		alignment = map_and_fenceable ? fence_alignment :

		alignment = map_and_fenceable ? fence_alignment :

drivers/gpu/drm/i915/i915_gem_tiling.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -374,9 +374,9 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, 
		/* Rebind if we need a change of alignment */

		/* Rebind if we need a change of alignment */

		if (!obj->map_and_fenceable) {

		if (!obj->map_and_fenceable) {

			u32 unfenced_alignment =

			u32 unfenced_alignment =

				i915_gem_get_unfenced_gtt_alignment(dev,

				i915_gem_get_gtt_alignment(dev, obj->base.size,

								    obj->base.size,

							    args->tiling_mode,

								    args->tiling_mode);

							    false);

			if (obj->gtt_offset & (unfenced_alignment - 1))

			if (obj->gtt_offset & (unfenced_alignment - 1))

				ret = i915_gem_object_unbind(obj);

				ret = i915_gem_object_unbind(obj);

		}

		}