Commit d8210e28 authored Aug 29, 2014 by Stephen Boyd Committed by Mike Turquette Sep 02, 2014

clk: qcom: Fix sdc 144kHz frequency entry

The pre-divider for the sdc clocks only has 2 bits in it, so we
can't possibly divide by anything larger than 4 here.
Furthermore, we program the value of ~(n - m) and the n value is
larger than 8 bits (max of 256). Replace this entry with 200kHz
which is close enough to 144kHz to be usable.

Cc: Kumar Gala <galak@codeaurora.org>
Cc: Andy Gross <agross@codeaurora.org>
Fixes: 24d8fba4 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

parent e8531ac8

drivers/clk/qcom/gcc-ipq806x.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1095,7 +1095,7 @@ static struct clk_branch prng_clk = {
		};

		static const struct freq_tbl clk_tbl_sdc[] = {
		{ 144000, P_PXO, 5, 18,625 },
		{ 200000, P_PXO, 2, 2, 125 },
		{ 400000, P_PLL8, 4, 1, 240 },
		{ 16000000, P_PLL8, 4, 1, 6 },
		{ 17070000, P_PLL8, 1, 2, 45 },