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Commit d783738c authored Jan 10, 2017 by Jaedon Shin Committed by Ralf Baechle Jan 24, 2017

MIPS: BMIPS: Add support SPI device nodes



Adds SPI device nodes to BCM7xxx MIPS based SoCs.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14990/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 35e7f788

arch/mips/boot/dts/brcm/bcm7125.dtsi

+46 −3

Original line number	Diff line number	Diff line
		@@ -91,15 +91,15 @@
		compatible = "brcm,bcm7120-l2-intc";
		reg = <0x406780 0x8>;

		brcm,int-map-mask = <0x44>, <0xf000000>;
		brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
		brcm,int-fwd-mask = <0x70000>;

		interrupt-controller;
		#interrupt-cells = <1>;

		interrupt-parent = <&periph_intc>;
		interrupts = <18>, <19>;
		interrupt-names = "upg_main", "upg_bsc";
		interrupts = <18>, <19>, <20>;
		interrupt-names = "upg_main", "upg_bsc", "upg_spi";
		};

		sun_top_ctrl: syscon@404000 {
		@@ -226,5 +226,48 @@
		interrupts = <61>;
		status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
		compatible = "brcm,l2-intc";
		reg = <0x411d00 0x30>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&periph_intc>;
		interrupts = <79>;
		};

		qspi: spi@443000 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-qspi";
		clocks = <&upg_clk>;
		reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
		reg-names = "cs_reg", "hif_mspi", "bspi";
		interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
		interrupt-parent = <&spi_l2_intc>;
		interrupt-names = "spi_lr_fullness_reached",
		"spi_lr_session_aborted",
		"spi_lr_impatient",
		"spi_lr_session_done",
		"spi_lr_overread",
		"mspi_done",
		"mspi_halted";
		status = "disabled";
		};

		mspi: spi@406400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-mspi";
		clocks = <&upg_clk>;
		reg = <0x406400 0x180>;
		reg-names = "mspi";
		interrupts = <0x14>;
		interrupt-parent = <&upg_irq0_intc>;
		interrupt-names = "mspi_done";
		status = "disabled";
		};
		};
		};

arch/mips/boot/dts/brcm/bcm7346.dtsi

+43 −0

Original line number	Diff line number	Diff line
		@@ -439,5 +439,48 @@
		interrupts = <85>;
		status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
		compatible = "brcm,l2-intc";
		reg = <0x411d00 0x30>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&periph_intc>;
		interrupts = <31>;
		};

		qspi: spi@413000 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-qspi";
		clocks = <&upg_clk>;
		reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
		reg-names = "cs_reg", "hif_mspi", "bspi";
		interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
		interrupt-parent = <&spi_l2_intc>;
		interrupt-names = "spi_lr_fullness_reached",
		"spi_lr_session_aborted",
		"spi_lr_impatient",
		"spi_lr_session_done",
		"spi_lr_overread",
		"mspi_done",
		"mspi_halted";
		status = "disabled";
		};

		mspi: spi@408a00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-mspi";
		clocks = <&upg_clk>;
		reg = <0x408a00 0x180>;
		reg-names = "mspi";
		interrupts = <0x14>;
		interrupt-parent = <&upg_aon_irq0_intc>;
		interrupt-names = "mspi_done";
		status = "disabled";
		};
		};
		};

arch/mips/boot/dts/brcm/bcm7358.dtsi

+43 −0

Original line number	Diff line number	Diff line
		@@ -318,5 +318,48 @@
		interrupts = <24>;
		status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
		compatible = "brcm,l2-intc";
		reg = <0x411d00 0x30>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&periph_intc>;
		interrupts = <31>;
		};

		qspi: spi@413000 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-qspi";
		clocks = <&upg_clk>;
		reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
		reg-names = "cs_reg", "hif_mspi", "bspi";
		interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
		interrupt-parent = <&spi_l2_intc>;
		interrupt-names = "spi_lr_fullness_reached",
		"spi_lr_session_aborted",
		"spi_lr_impatient",
		"spi_lr_session_done",
		"spi_lr_overread",
		"mspi_done",
		"mspi_halted";
		status = "disabled";
		};

		mspi: spi@408a00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-mspi";
		clocks = <&upg_clk>;
		reg = <0x408a00 0x180>;
		reg-names = "mspi";
		interrupts = <0x14>;
		interrupt-parent = <&upg_aon_irq0_intc>;
		interrupt-names = "mspi_done";
		status = "disabled";
		};
		};
		};

arch/mips/boot/dts/brcm/bcm7360.dtsi

+43 −0

Original line number	Diff line number	Diff line
		@@ -358,5 +358,48 @@
		interrupts = <82>;
		status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
		compatible = "brcm,l2-intc";
		reg = <0x411d00 0x30>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&periph_intc>;
		interrupts = <31>;
		};

		qspi: spi@413000 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-qspi";
		clocks = <&upg_clk>;
		reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
		reg-names = "cs_reg", "hif_mspi", "bspi";
		interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
		interrupt-parent = <&spi_l2_intc>;
		interrupt-names = "spi_lr_fullness_reached",
		"spi_lr_session_aborted",
		"spi_lr_impatient",
		"spi_lr_session_done",
		"spi_lr_overread",
		"mspi_done",
		"mspi_halted";
		status = "disabled";
		};

		mspi: spi@408a00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-mspi";
		clocks = <&upg_clk>;
		reg = <0x408a00 0x180>;
		reg-names = "mspi";
		interrupts = <0x14>;
		interrupt-parent = <&upg_aon_irq0_intc>;
		interrupt-names = "mspi_done";
		status = "disabled";
		};
		};
		};

arch/mips/boot/dts/brcm/bcm7362.dtsi

+43 −0

Original line number	Diff line number	Diff line
		@@ -354,5 +354,48 @@
		interrupts = <82>;
		status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
		compatible = "brcm,l2-intc";
		reg = <0x411d00 0x30>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&periph_intc>;
		interrupts = <31>;
		};

		qspi: spi@413000 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-qspi";
		clocks = <&upg_clk>;
		reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
		reg-names = "cs_reg", "hif_mspi", "bspi";
		interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
		interrupt-parent = <&spi_l2_intc>;
		interrupt-names = "spi_lr_fullness_reached",
		"spi_lr_session_aborted",
		"spi_lr_impatient",
		"spi_lr_session_done",
		"spi_lr_overread",
		"mspi_done",
		"mspi_halted";
		status = "disabled";
		};

		mspi: spi@408a00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "brcm,spi-bcm-qspi",
		"brcm,spi-brcmstb-mspi";
		clocks = <&upg_clk>;
		reg = <0x408a00 0x180>;
		reg-names = "mspi";
		interrupts = <0x14>;
		interrupt-parent = <&upg_aon_irq0_intc>;
		interrupt-names = "mspi_done";
		status = "disabled";
		};
		};
		};