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Commit d6f945be authored by Ram Chandrasekar's avatar Ram Chandrasekar
Browse files

ARM: dts: msm: Add LMH-DCVSh configuration for sdm855 



Add LMH-DCVSh hardware configuration like debug interrupt and cluster
affinity value for sdm855. Add the CPU to LMH-DCVSh hardware
mapping, along with the thermal algorithm configuration.

Change-Id: I8eb893ac41d8ca5a4f2e71425003140ce11e91bd
Signed-off-by: default avatarRam Chandrasekar <rkumbako@codeaurora.org>
parent 5c5260ab

arch/arm64/boot/dts/qcom/sdm855-thermal.dtsi

+52 −0
Original line number Diff line number Diff line
@@ -12,6 +12,28 @@ 


#include <dt-bindings/thermal/thermal.h>



&clock_cpucc {

	#address-cells = <1>;

	#size-cells = <1>;

	lmh_dcvs0: qcom,limits-dcvs@18358800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18323000 0x1000>;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18325800 0x1000>;

		#thermal-sensor-cells = <0>;

	};

};



&thermal_zones {

	aoss0-usr {

		polling-delay-passive = <0>;
@@ -444,4 +466,34 @@ 
			};

		};

	};



	lmh-dcvs-01 {

		polling-delay-passive = <0>;

		polling-delay = <0>;

		thermal-governor = "user_space";

		thermal-sensors = <&lmh_dcvs1>;



		trips {

			active-config {

				temperature = <95000>;

				hysteresis = <30000>;

				type = "passive";

			};

		};

	};



	lmh-dcvs-00 {

		polling-delay-passive = <0>;

		polling-delay = <0>;

		thermal-governor = "user_space";

		thermal-sensors = <&lmh_dcvs0>;



		trips {

			active-config {

				temperature = <95000>;

				hysteresis = <30000>;

				type = "passive";

			};

		};

	};

};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ 
			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -97,6 +98,7 @@ 
			cache-size = <0x8000>;

			next-level-cache = <&L2_1>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -129,6 +131,7 @@ 
			cache-size = <0x8000>;

			next-level-cache = <&L2_2>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";
@@ -161,6 +164,7 @@ 
			cache-size = <0x8000>;

			next-level-cache = <&L2_3>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";
@@ -193,6 +197,7 @@ 
			cache-size = <0x20000>;

			next-level-cache = <&L2_4>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";
@@ -225,6 +230,7 @@ 
			cache-size = <0x20000>;

			next-level-cache = <&L2_5>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";
@@ -257,6 +263,7 @@ 
			cache-size = <0x20000>;

			next-level-cache = <&L2_6>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";
@@ -289,6 +296,7 @@ 
			cache-size = <0x20000>;

			next-level-cache = <&L2_7>;

			sched-energy-costs = <&CPU_COST_2 &CLUSTER_COST_2>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";