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Commit d6db995f authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer disables there 



Move the CHV clock buffer disable from chv_disable_pll() to the new
encoder .post_pll_disable() hook. This is more symmetric since the
clock buffer enable happens from the .pre_pll_enable() hook.

We'll have more use for the new hook soon.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 67fa24b4

drivers/gpu/drm/i915/intel_display.c

+4 −11
Original line number Diff line number Diff line
@@ -1828,17 +1828,6 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 
	val &= ~DPIO_DCLKP_EN;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->sb_lock);

}
@@ -6193,6 +6182,10 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) 
			i9xx_disable_pll(intel_crtc);

	}



	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->post_pll_disable)

			encoder->post_pll_disable(encoder);



	if (!IS_GEN2(dev))

		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

drivers/gpu/drm/i915/intel_dp.c

+23 −0
Original line number Diff line number Diff line
@@ -2943,6 +2943,28 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 
	mutex_unlock(&dev_priv->sb_lock);

}



static void chv_dp_post_pll_disable(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->sb_lock);

}



/*

 * Native read with retry for link status and receiver capability reads for

 * cases where the sink may still be asleep.
@@ -6000,6 +6022,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 
		intel_encoder->pre_enable = chv_pre_enable_dp;

		intel_encoder->enable = vlv_enable_dp;

		intel_encoder->post_disable = chv_post_disable_dp;

		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;

	} else if (IS_VALLEYVIEW(dev)) {

		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;

		intel_encoder->pre_enable = vlv_pre_enable_dp;

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ struct intel_encoder { 
	void (*mode_set)(struct intel_encoder *intel_encoder);

	void (*disable)(struct intel_encoder *);

	void (*post_disable)(struct intel_encoder *);

	void (*post_pll_disable)(struct intel_encoder *);

	/* Read out the current hw state of this connector, returning true if

	 * the encoder is active. If the encoder is enabled it also set the pipe

	 * it is connected to in the pipe parameter. */

drivers/gpu/drm/i915/intel_hdmi.c

+23 −0
Original line number Diff line number Diff line
@@ -1681,6 +1681,28 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 
	mutex_unlock(&dev_priv->sb_lock);

}



static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->sb_lock);

}



static void vlv_hdmi_post_disable(struct intel_encoder *encoder)

{

	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
@@ -2083,6 +2105,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) 
		intel_encoder->pre_enable = chv_hdmi_pre_enable;

		intel_encoder->enable = vlv_enable_hdmi;

		intel_encoder->post_disable = chv_hdmi_post_disable;

		intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;

	} else if (IS_VALLEYVIEW(dev)) {

		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;

		intel_encoder->pre_enable = vlv_hdmi_pre_enable;