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Commit d56676a2 authored by Shubhashree Dhar's avatar Shubhashree Dhar
Browse files

drm/msm/sde: add qdss config structure in display driver 



Add qdss config structure in sde display driver.

Change-Id: I6c095cacb2359eda7e766b8af569e25714169bdb
Signed-off-by: default avatarShubhashree Dhar <dhar@codeaurora.org>
parent 22aaa275

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+14 −0
Original line number Diff line number Diff line
@@ -836,6 +836,17 @@ struct sde_merge_3d_cfg { 
	SDE_HW_BLK_INFO;

};



/**

 * struct sde_qdss_cfg - information of qdss blocks

 * @id                 enum identifying this block

 * @base               register offset of this block

 * @len:               length of hardware block

 * @features           bit mask identifying sub-blocks/features

 */

struct sde_qdss_cfg {

	SDE_HW_BLK_INFO;

};



/**

 * struct sde_rot_vbif_cfg - inline rotator vbif configs

 * @xin_id             xin client id
@@ -1178,6 +1189,9 @@ struct sde_mdss_cfg { 
	u32 merge_3d_count;

	struct sde_merge_3d_cfg merge_3d[MAX_BLOCKS];



	u32 qdss_count;

	struct sde_qdss_cfg qdss[MAX_BLOCKS];



	/* Add additional block data structures here */



	struct sde_perf_cfg perf;

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+8 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -112,6 +112,7 @@ enum sde_hw_blk_type { 
	SDE_HW_BLK_DSC,

	SDE_HW_BLK_ROT,

	SDE_HW_BLK_MERGE_3D,

	SDE_HW_BLK_QDSS,

	SDE_HW_BLK_MAX,

};
@@ -326,6 +327,11 @@ enum sde_merge_3d { 
	MERGE_3D_MAX

};



enum sde_qdss {

	QDSS_0,

	QDSS_MAX

};



/**

 * SDE HW,Component order color map

 */
@@ -514,6 +520,7 @@ struct sde_mdss_color { 
#define SDE_DBG_MASK_ROT      (1 << 12)

#define SDE_DBG_MASK_DS       (1 << 13)

#define SDE_DBG_MASK_REGDMA   (1 << 14)

#define SDE_DBG_MASK_QDSS     (1 << 15)



/**

 * struct sde_hw_cp_cfg: hardware dspp/lm feature payload.