Loading drivers/gpu/drm/i915/i915_reg.h +2 −5 Original line number Original line Diff line number Diff line Loading @@ -5439,9 +5439,7 @@ enum { #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) #define MCURSOR_PIPE_SELECT (1 << 28) #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) #define MCURSOR_PIPE_A 0x00 #define MCURSOR_PIPE_B (1 << 28) #define MCURSOR_GAMMA_ENABLE (1 << 26) #define MCURSOR_GAMMA_ENABLE (1 << 26) #define CURSOR_ROTATE_180 (1<<15) #define CURSOR_ROTATE_180 (1<<15) #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) Loading Loading @@ -5499,8 +5497,7 @@ enum { #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) #define DISPPLANE_SEL_PIPE_SHIFT 24 #define DISPPLANE_SEL_PIPE_SHIFT 24 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SEL_PIPE_A 0 #define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SRC_KEY_ENABLE (1<<22) #define DISPPLANE_SRC_KEY_ENABLE (1<<22) #define DISPPLANE_SRC_KEY_DISABLE 0 #define DISPPLANE_SRC_KEY_DISABLE 0 #define DISPPLANE_LINE_DOUBLE (1<<20) #define DISPPLANE_LINE_DOUBLE (1<<20) Loading drivers/gpu/drm/i915/intel_display.c +3 −6 Original line number Original line Diff line number Diff line Loading @@ -2981,10 +2981,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; if (INTEL_GEN(dev_priv) < 4) { if (INTEL_GEN(dev_priv) < 4) if (crtc->pipe == PIPE_B) dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); dspcntr |= DISPPLANE_SEL_PIPE_B; } switch (fb->format->format) { switch (fb->format->format) { case DRM_FORMAT_C8: case DRM_FORMAT_C8: Loading Loading @@ -9217,7 +9215,6 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, struct drm_i915_private *dev_priv = struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); to_i915(plane_state->base.plane->dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); enum pipe pipe = crtc->pipe; u32 cntl; u32 cntl; cntl = MCURSOR_GAMMA_ENABLE; cntl = MCURSOR_GAMMA_ENABLE; Loading @@ -9225,7 +9222,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, if (HAS_DDI(dev_priv)) if (HAS_DDI(dev_priv)) cntl |= CURSOR_PIPE_CSC_ENABLE; cntl |= CURSOR_PIPE_CSC_ENABLE; cntl |= pipe << 28; /* Connect to correct pipe */ cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); switch (plane_state->base.crtc_w) { switch (plane_state->base.crtc_w) { case 64: case 64: Loading Loading
drivers/gpu/drm/i915/i915_reg.h +2 −5 Original line number Original line Diff line number Diff line Loading @@ -5439,9 +5439,7 @@ enum { #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) #define MCURSOR_PIPE_SELECT (1 << 28) #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) #define MCURSOR_PIPE_A 0x00 #define MCURSOR_PIPE_B (1 << 28) #define MCURSOR_GAMMA_ENABLE (1 << 26) #define MCURSOR_GAMMA_ENABLE (1 << 26) #define CURSOR_ROTATE_180 (1<<15) #define CURSOR_ROTATE_180 (1<<15) #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) Loading Loading @@ -5499,8 +5497,7 @@ enum { #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) #define DISPPLANE_SEL_PIPE_SHIFT 24 #define DISPPLANE_SEL_PIPE_SHIFT 24 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SEL_PIPE_A 0 #define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) #define DISPPLANE_SRC_KEY_ENABLE (1<<22) #define DISPPLANE_SRC_KEY_ENABLE (1<<22) #define DISPPLANE_SRC_KEY_DISABLE 0 #define DISPPLANE_SRC_KEY_DISABLE 0 #define DISPPLANE_LINE_DOUBLE (1<<20) #define DISPPLANE_LINE_DOUBLE (1<<20) Loading
drivers/gpu/drm/i915/intel_display.c +3 −6 Original line number Original line Diff line number Diff line Loading @@ -2981,10 +2981,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; if (INTEL_GEN(dev_priv) < 4) { if (INTEL_GEN(dev_priv) < 4) if (crtc->pipe == PIPE_B) dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); dspcntr |= DISPPLANE_SEL_PIPE_B; } switch (fb->format->format) { switch (fb->format->format) { case DRM_FORMAT_C8: case DRM_FORMAT_C8: Loading Loading @@ -9217,7 +9215,6 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, struct drm_i915_private *dev_priv = struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); to_i915(plane_state->base.plane->dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); enum pipe pipe = crtc->pipe; u32 cntl; u32 cntl; cntl = MCURSOR_GAMMA_ENABLE; cntl = MCURSOR_GAMMA_ENABLE; Loading @@ -9225,7 +9222,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, if (HAS_DDI(dev_priv)) if (HAS_DDI(dev_priv)) cntl |= CURSOR_PIPE_CSC_ENABLE; cntl |= CURSOR_PIPE_CSC_ENABLE; cntl |= pipe << 28; /* Connect to correct pipe */ cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); switch (plane_state->base.crtc_w) { switch (plane_state->base.crtc_w) { case 64: case 64: Loading