Merge "clk: qcom: Add measure-only graphic clocks for sdm855" into msm-4.14 (d4d83da1) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/gpucc-sdm855.c

+44 −1

Original line number	Diff line number	Diff line
		@@ -374,6 +374,42 @@ static struct clk_branch gpu_cc_sleep_clk = {
		},
		};

		/* Measure-only clock for gpu_cc_cx_gfx3d_clk. */
		static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_clk = {
		.rrate = 1000,
		.hw.init = &(struct clk_init_data){
		.name = "measure_only_gpu_cc_cx_gfx3d_clk",
		.ops = &clk_dummy_ops,
		},
		};

		/* Measure-only clock for gpu_cc_cx_gfx3d_slv_clk. */
		static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_slv_clk = {
		.rrate = 1000,
		.hw.init = &(struct clk_init_data){
		.name = "measure_only_gpu_cc_cx_gfx3d_slv_clk",
		.ops = &clk_dummy_ops,
		},
		};

		/* Measure-only clock for gpu_cc_gx_gfx3d_clk. */
		static struct clk_dummy measure_only_gpu_cc_gx_gfx3d_clk = {
		.rrate = 1000,
		.hw.init = &(struct clk_init_data){
		.name = "measure_only_gpu_cc_gx_gfx3d_clk",
		.ops = &clk_dummy_ops,
		},
		};

		struct clk_hw *gpu_cc_sdm855_hws[] = {
		[MEASURE_ONLY_GPU_CC_CX_GFX3D_CLK] =
		&measure_only_gpu_cc_cx_gfx3d_clk.hw,
		[MEASURE_ONLY_GPU_CC_CX_GFX3D_SLV_CLK] =
		&measure_only_gpu_cc_cx_gfx3d_slv_clk.hw,
		[MEASURE_ONLY_GPU_CC_GX_GFX3D_CLK] =
		&measure_only_gpu_cc_gx_gfx3d_clk.hw,
		};

		static struct clk_regmap *gpu_cc_sdm855_clocks[] = {
		[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
		[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
		@@ -453,7 +489,8 @@ static int gpu_cc_sdm855_fixup(struct platform_device *pdev)
		static int gpu_cc_sdm855_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;
		int ret = 0;
		struct clk *clk;
		int i, ret = 0;

		regmap = qcom_cc_map(pdev, &gpu_cc_sdm855_desc);
		if (IS_ERR(regmap))
		@@ -479,6 +516,12 @@ static int gpu_cc_sdm855_probe(struct platform_device *pdev)

		gpu_cc_sdm855_fixup(pdev);

		for (i = 0; i < ARRAY_SIZE(gpu_cc_sdm855_hws); i++) {
		clk = devm_clk_register(&pdev->dev, gpu_cc_sdm855_hws[i]);
		if (IS_ERR(clk))
		return PTR_ERR(clk);
		}

		ret = qcom_cc_really_probe(pdev, &gpu_cc_sdm855_desc, regmap);
		if (ret) {
		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");

include/dt-bindings/clock/qcom,gpucc-sdm855.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -44,4 +44,9 @@
		#define GPUCC_GPU_CC_SPDM_BCR 5
		#define GPUCC_GPU_CC_XO_BCR 6

		/* Dummy clocks for rate measurement */
		#define MEASURE_ONLY_GPU_CC_CX_GFX3D_CLK 0
		#define MEASURE_ONLY_GPU_CC_CX_GFX3D_SLV_CLK 1
		#define MEASURE_ONLY_GPU_CC_GX_GFX3D_CLK 2

		#endif