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Commit d4946ccf authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu: new method to sync ce&de 



sync switch buffer scheme with windows kmd for gfx v8,
step2:
Insert 128NOP after&before VM flush to prevent CE vm fault.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ea4a8c1d

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+6 −18
Original line number Diff line number Diff line
@@ -5911,12 +5911,6 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 
{

	u32 header, control = 0;



	/* insert SWITCH_BUFFER packet before first IB in the ring frame */

	if (ctx_switch) {

		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

		amdgpu_ring_write(ring, 0);

	}



	if (ib->flags & AMDGPU_IB_FLAG_CE)

		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);

	else
@@ -5986,14 +5980,6 @@ static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, seq);

	amdgpu_ring_write(ring, 0xffffffff);

	amdgpu_ring_write(ring, 4); /* poll interval */



	if (usepfp) {

		/* synce CE with ME to prevent CE fetch CEIB before context switch done */

		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

		amdgpu_ring_write(ring, 0);

		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

		amdgpu_ring_write(ring, 0);

	}

}



static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
@@ -6001,6 +5987,10 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 
{

	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);



	/* GFX8 emits 128 dw nop to prevent DE do vm_flush before CE finish CEIB */

	if (usepfp)

		amdgpu_ring_insert_nop(ring, 128);



	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |

				 WRITE_DATA_DST_SEL(0)) |
@@ -6040,10 +6030,8 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 
		/* sync PFP to ME, otherwise we might get invalid PFP reads */

		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

		amdgpu_ring_write(ring, 0x0);

		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

		amdgpu_ring_write(ring, 0);

		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

		amdgpu_ring_write(ring, 0);

		/* GFX8 emits 128 dw nop to prevent CE access VM before vm_flush finish */

		amdgpu_ring_insert_nop(ring, 128);

	}

}