Loading arch/arm64/boot/dts/qcom/sdm855.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -50,6 +50,7 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_0>; L2_0: l2-cache { Loading Loading @@ -85,6 +86,7 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_1>; L2_1: l2-cache { Loading Loading @@ -114,6 +116,7 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_2>; L2_2: l2-cache { Loading Loading @@ -143,6 +146,7 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_3>; L2_3: l2-cache { Loading Loading @@ -172,6 +176,7 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_4>; L2_4: l2-cache { Loading Loading @@ -201,6 +206,7 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_5>; L2_5: l2-cache { Loading Loading @@ -230,6 +236,7 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_6>; L2_6: l2-cache { Loading Loading @@ -259,6 +266,7 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_7>; L2_7: l2-cache { Loading Loading
arch/arm64/boot/dts/qcom/sdm855.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -50,6 +50,7 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_0>; L2_0: l2-cache { Loading Loading @@ -85,6 +86,7 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_1>; L2_1: l2-cache { Loading Loading @@ -114,6 +116,7 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_2>; L2_2: l2-cache { Loading Loading @@ -143,6 +146,7 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_3>; L2_3: l2-cache { Loading Loading @@ -172,6 +176,7 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_4>; L2_4: l2-cache { Loading Loading @@ -201,6 +206,7 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_5>; L2_5: l2-cache { Loading Loading @@ -230,6 +236,7 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_6>; L2_6: l2-cache { Loading Loading @@ -259,6 +266,7 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_7>; L2_7: l2-cache { Loading