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Commit d3d6d927 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Change display rsc to use AWAKE votes for ATOLL"

parents 263f453b 443c3fc4
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+1994 −0

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+1 −0
Original line number Diff line number Diff line
@@ -2355,6 +2355,7 @@
#include "msm-arm-smmu-atoll.dtsi"
#include "atoll-qupv3.dtsi"
#include "sdmmagpie-gpu.dtsi"
#include "atoll-bus.dtsi"

&msm_gpu {
	/delete-property/qcom,gpu-speed-bin;
+28 −11
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@
#define	MSM_BUS_FAB_GPU_VIRT 6158
#define	MSM_BUS_FAB_MMNRT_VIRT 6159
#define	MSM_BUS_FAB_MMRT_VIRT 6160
#define	MSM_BUS_FAB_NPU_NOC 6161

#define	MSM_BUS_FAB_MC_VIRT_DISPLAY 26000
#define	MSM_BUS_FAB_MEM_NOC_DISPLAY 26001
@@ -100,16 +101,17 @@
#define	MSM_BUS_BCM_CO0 7041
#define	MSM_BUS_BCM_CO1 7042
#define	MSM_BUS_BCM_CO2 7043
#define	MSM_BUS_BCM_QP0 7044
#define	MSM_BUS_BCM_PN0 7045
#define	MSM_BUS_BCM_PN1 7046
#define	MSM_BUS_BCM_PN2 7047
#define	MSM_BUS_BCM_PN3 7048
#define	MSM_BUS_BCM_PN4 7049
#define	MSM_BUS_BCM_PN5 7050
#define	MSM_BUS_BCM_SH8 7051
#define	MSM_BUS_BCM_SH9 7052
#define	MSM_BUS_BCM_SH10 7053
#define	MSM_BUS_BCM_CO3 7044
#define	MSM_BUS_BCM_QP0 7045
#define	MSM_BUS_BCM_PN0 7046
#define	MSM_BUS_BCM_PN1 7047
#define	MSM_BUS_BCM_PN2 7048
#define	MSM_BUS_BCM_PN3 7049
#define	MSM_BUS_BCM_PN4 7050
#define	MSM_BUS_BCM_PN5 7051
#define	MSM_BUS_BCM_SH8 7052
#define	MSM_BUS_BCM_SH9 7053
#define	MSM_BUS_BCM_SH10 7054

#define	MSM_BUS_RSC_APPS 8000
#define	MSM_BUS_RSC_DISP 8001
@@ -308,6 +310,8 @@
#define	MSM_BUS_MASTER_GPU_CDSP_PROC 182
#define	MSM_BUS_MASTER_QUP_CORE_0 183
#define	MSM_BUS_MASTER_QUP_CORE_1 184
#define	MSM_BUS_MASTER_NPU_PROC 185
#define	MSM_BUS_MASTER_NPU_SYS 186

#define	MSM_BUS_MASTER_LLCC_DISPLAY 20000
#define	MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY 20001
@@ -699,6 +703,19 @@
#define	MSM_BUS_SLAVE_GPU_CDSP_BIMC 820
#define	MSM_BUS_SLAVE_QM_MPU_CFG 821
#define	MSM_BUS_SLAVE_CDSP_THROTTLE_CFG 822
#define	MSM_BUS_MASTER_NPU_NOC_CFG 823
#define	MSM_BUS_SLAVE_NPU_CAL_DP0 824
#define	MSM_BUS_SLAVE_NPU_CP 825
#define	MSM_BUS_SLAVE_NPU_INT_DMA_BWMON_CFG 826
#define	MSM_BUS_SLAVE_NPU_DPM 827
#define	MSM_BUS_SLAVE_ISENSE_CFG 828
#define	MSM_BUS_SLAVE_NPU_LLM_CFG 829
#define	MSM_BUS_SLAVE_NPU_TCM 830
#define	MSM_BUS_SLAVE_NPU_COMPUTE_NOC 831
#define	MSM_BUS_SLAVE_SERVICE_NPU_NOC 832
#define	MSM_BUS_SLAVE_DISPLAY_RT_THROTTLE_CFG 833
#define	MSM_BUS_SLAVE_NPU_DMA_BWMON_CFG 834
#define	MSM_BUS_SLAVE_NPU_PROC_BWMON_CFG 835

#define	MSM_BUS_SLAVE_EBI_CH0_DISPLAY 20512
#define	MSM_BUS_SLAVE_LLCC_DISPLAY 20513