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Commit d3cb155e authored by Thomas (Wonyoung) Yun's avatar Thomas (Wonyoung) Yun
Browse files

msm: Configure UCHE GMEM base address based on GMEM size 



Different ASIC can have a different GMEM size so need to configure
a UCHE GMEM base address accordingly.

Change-Id: I97e70e5ef36374cf9f0bff88613e9f3f940ff846
Signed-off-by: default avatarThomas (Wonyoung) Yun <wyun@codeaurora.org>
parent 99d87c60

drivers/gpu/msm/adreno.c

+2 −2
Original line number Diff line number Diff line
@@ -834,7 +834,7 @@ adreno_identify_gpu(struct adreno_device *adreno_dev) 
	 */



	adreno_dev->gmem_size = adreno_dev->gpucore->gmem_size;



	adreno_dev->uche_gmem_base = ALIGN(adreno_dev->gmem_size, SZ_4K);

	/*

	 * Initialize uninitialzed gpu registers, only needs to be done once

	 * Make all offsets that are not initialized to ADRENO_REG_UNUSED
@@ -2546,7 +2546,7 @@ static int adreno_getproperty(struct kgsl_device *device, 


			if (adreno_is_a5xx(adreno_dev) ||

					adreno_is_a6xx(adreno_dev))

				gmem_vaddr = ADRENO_UCHE_GMEM_BASE;

				gmem_vaddr = adreno_dev->uche_gmem_base;

			if (sizebytes != sizeof(uint64_t)) {

				status = -EINVAL;

				break;

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -444,6 +444,7 @@ enum gpu_coresight_sources { 
 * @chipid: Chip ID specific to the GPU

 * @gmem_base: Base physical address of GMEM

 * @gmem_size: GMEM size

 * @uche_gmem_base: Base physical address of UCHE GMEM

 * @qdss_gfx_base: Base physical address of QDSS_GFX_DBG registers for Coresight

 * @qdss_gfx_len: QDSS_GFX_DBG register size

 * @qdss_gfx_virt: Pointer to virtual address of QDSS_GFX_DBG regiter
@@ -527,6 +528,7 @@ struct adreno_device { 
	unsigned int chipid;

	unsigned long gmem_base;

	unsigned long gmem_size;

	unsigned long uche_gmem_base;

	unsigned long qdss_gfx_base;

	unsigned long qdss_gfx_len;

	void __iomem *qdss_gfx_virt;

drivers/gpu/msm/adreno_a6xx.c

+4 −3
Original line number Diff line number Diff line
@@ -818,10 +818,10 @@ static void a6xx_start(struct adreno_device *adreno_dev) 


	/* Program the GMEM VA range for the UCHE path */

	kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_LO,

				ADRENO_UCHE_GMEM_BASE);

				adreno_dev->uche_gmem_base);

	kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);

	kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_LO,

				ADRENO_UCHE_GMEM_BASE +

				adreno_dev->uche_gmem_base +

				adreno_dev->gmem_size - 1);

	kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);
@@ -2908,7 +2908,8 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev) 
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	/* Calculate SP local and private mem addresses */

	addr = ALIGN(ADRENO_UCHE_GMEM_BASE + adreno_dev->gmem_size, SZ_64K);

	addr = ALIGN(adreno_dev->uche_gmem_base + adreno_dev->gmem_size,

					SZ_64K);

	adreno_dev->sp_local_gpuaddr = addr;

	adreno_dev->sp_pvt_gpuaddr = addr + SZ_64K;