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Commit d2d0714a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add emmc and sdcard device node for atoll"

parents d4ba9fc3 5c615071

arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi

+138 −0
Original line number Diff line number Diff line
@@ -21,6 +21,144 @@ 
		interrupt-controller;

		#interrupt-cells = <2>;



		/* SDC pin type */

		sdc1_clk_on: sdc1_clk_on {

			config {

				pins = "sdc1_clk";

				bias-disable;		/* NO pull */

				drive-strength = <16>;	/* 16 MA */

			};

		};



		sdc1_clk_off: sdc1_clk_off {

			config {

				pins = "sdc1_clk";

				bias-disable;		/* NO pull */

				drive-strength = <2>;	/* 2 MA */

			};

		};



		sdc1_cmd_on: sdc1_cmd_on {

			config {

				pins = "sdc1_cmd";

				bias-pull-up;		/* pull up */

				drive-strength = <10>;	/* 10 MA */

			};

		};



		sdc1_cmd_off: sdc1_cmd_off {

			config {

				pins = "sdc1_cmd";

				num-grp-pins = <1>;

				bias-pull-up;		/* pull up */

				drive-strength = <2>;	/* 2 MA */

			};

		};



		sdc1_data_on: sdc1_data_on {

			config {

				pins = "sdc1_data";

				bias-pull-up;		/* pull up */

				drive-strength = <10>;	/* 10 MA */

			};

		};



		sdc1_data_off: sdc1_data_off {

			config {

				pins = "sdc1_data";

				bias-pull-up;		/* pull up */

				drive-strength = <2>;	/* 2 MA */

			};

		};



		sdc1_rclk_on: sdc1_rclk_on {

			config {

				pins = "sdc1_rclk";

				bias-pull-down; /* pull down */

			};

		};



		sdc1_rclk_off: sdc1_rclk_off {

			config {

				pins = "sdc1_rclk";

				bias-pull-down; /* pull down */

			};

		};



		sdc2_clk_on: sdc2_clk_on {

			config {

				pins = "sdc2_clk";

				bias-disable;		/* NO pull */

				drive-strength = <16>;	/* 16 MA */

			};

		};



		sdc2_clk_off: sdc2_clk_off {

			config {

				pins = "sdc2_clk";

				bias-disable;		/* NO pull */

				drive-strength = <2>;	/* 2 MA */

			};

		};



		sdc2_cmd_on: sdc2_cmd_on {

			config {

				pins = "sdc2_cmd";

				bias-pull-up;		/* pull up */

				drive-strength = <10>;	/* 10 MA */

			};

		};



		sdc2_cmd_off: sdc2_cmd_off {

			config {

				pins = "sdc2_cmd";

				bias-pull-up;		/* pull up */

				drive-strength = <2>;	/* 2 MA */

			};

		};



		sdc2_data_on: sdc2_data_on {

			config {

				pins = "sdc2_data";

				bias-pull-up;		/* pull up */

				drive-strength = <10>;	/* 10 MA */

			};

		};



		sdc2_data_off: sdc2_data_off {

			config {

				pins = "sdc2_data";

				bias-pull-up;		/* pull up */

				drive-strength = <2>;	/* 2 MA */

			};

		};



		sdc2_cd_on: cd_on {

			mux {

				pins = "gpio69";

				function = "gpio";

			};



			config {

				pins = "gpio69";

				drive-strength = <2>;

				bias-pull-up;

			};

		};



		sdc2_cd_off: cd_off {

			mux {

				pins = "gpio69";

				function = "gpio";

			};



		config {

				pins = "gpio69";

				drive-strength = <2>;

				bias-disable;

			};

		};



		qupv3_se8_2uart_pins: qupv3_se8_2uart_pins {

			qupv3_se8_2uart_active: qupv3_se8_2uart_active {

				mux {

arch/arm64/boot/dts/qcom/atoll-rumi.dtsi

+48 −0
Original line number Diff line number Diff line
@@ -53,6 +53,54 @@ 
	};

};



#include "atoll-stub-regulator.dtsi"



&sdhc_1 {

	vdd-supply = <&pm6150_l19>;

	qcom,vdd-voltage-level = <2950000 2950000>;

	qcom,vdd-current-level = <0 570000>;



	vdd-io-supply = <&pm6150_l12>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <0 325000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on

					&sdc1_rclk_on>;

	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off

					&sdc1_rclk_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000>;

	qcom,bus-speed-mode = "DDR_1p8v";



	/delete-property/qcom,devfreq,freq-table;



	status = "ok";

};



&sdhc_2 {

	vdd-supply = <&pm6150l_l9>;

	qcom,vdd-voltage-level = <2960000 2960000>;

	qcom,vdd-current-level = <0 800000>;



	vdd-io-supply = <&pm6150l_l6>;

	qcom,vdd-io-voltage-level = <1800000 2950000>;

	qcom,vdd-io-current-level = <0 22000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on>;

	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000>;

	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";



	/delete-property/qcom,devfreq,freq-table;



	status = "ok";

};



&usb0 {

	dwc3@a600000 {

		usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;

arch/arm64/boot/dts/qcom/atoll.dtsi

+65 −0
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ 


	aliases {

		serial0 = &qupv3_se8_2uart;

		sdhc1 = &sdhc_1; /* eMMC */

		sdhc2 = &sdhc_2; /* SD Card */

	};



	cpus {
@@ -1587,6 +1589,69 @@ 
				  <CONTROL_TCS 1>;

	};



	sdhc_1: sdhci@7c4000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;

		reg-names = "hc_mem", "cmdq_mem";



		interrupts = <GIC_SPI 641 IRQ_TYPE_NONE>,

					<GIC_SPI 644 IRQ_TYPE_NONE>;

		interrupt-names = "hc_irq", "pwr_irq";



		qcom,bus-width = <8>;

		qcom,large-address-bus;



		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000

						192000000 384000000>;

		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";



		qcom,devfreq,freq-table = <50000000 200000000>;



		clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,

			<&clock_gcc GCC_SDCC1_APPS_CLK>,

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk";



		qcom,ice-clk-rates = <300000000 100000000>;



		qcom,scaling-lower-bus-speed-mode = "DDR52";



		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */

		qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>;



		qcom,nonremovable;

		status = "disabled";

	};



	sdhc_2: sdhci@8804000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x8804000 0x1000>;

		reg-names = "hc_mem";



		interrupts = <GIC_SPI 204 IRQ_TYPE_NONE>,

					<GIC_SPI 222 IRQ_TYPE_NONE>;

		interrupt-names = "hc_irq", "pwr_irq";



		qcom,bus-width = <4>;

		qcom,large-address-bus;



		qcom,clk-rates = <400000 20000000 25000000

				50000000 100000000 202000000>;

		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",

				      "SDR104";



		qcom,devfreq,freq-table = <50000000 202000000>;



		clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,

			<&clock_gcc GCC_SDCC2_APPS_CLK>;

		clock-names = "iface_clk", "core_clk";



		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */

		qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>;



		status = "disabled";

	};



	disp_rsc: mailbox@af20000 {

		compatible = "qcom,tcs-drv";

		label = "display_rsc";