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Commit d2b41f74 authored by Will Deacon's avatar Will Deacon
Browse files

ARM: perf: index Xscale and ARMv6 event counters starting from zero 



Now that the ARMv7 PMU backend indexes event counters from zero, follow
suit and do the same for ARMv6 and Xscale.

Acked-by: default avatarJamie Iles <jamie@jamieiles.com>
Reviewed-by: default avatarJean Pihet <j-pihet@ti.com>
Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent c691bb62

arch/arm/kernel/perf_event_v6.c

+2 −2
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ enum armv6_perf_types { 
};



enum armv6_counters {

	ARMV6_CYCLE_COUNTER = 1,

	ARMV6_CYCLE_COUNTER = 0,

	ARMV6_COUNTER0,

	ARMV6_COUNTER1,

};
@@ -487,7 +487,7 @@ armv6pmu_handle_irq(int irq_num, 
	perf_sample_data_init(&data, 0);



	cpuc = &__get_cpu_var(cpu_hw_events);

	for (idx = 0; idx <= armpmu->num_events; ++idx) {

	for (idx = 0; idx < armpmu->num_events; ++idx) {

		struct perf_event *event = cpuc->events[idx];

		struct hw_perf_event *hwc;

arch/arm/kernel/perf_event_xscale.c

+3 −3
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ enum xscale_perf_types { 
};



enum xscale_counters {

	XSCALE_CYCLE_COUNTER	= 1,

	XSCALE_CYCLE_COUNTER	= 0,

	XSCALE_COUNTER0,

	XSCALE_COUNTER1,

	XSCALE_COUNTER2,
@@ -249,7 +249,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev) 
	perf_sample_data_init(&data, 0);



	cpuc = &__get_cpu_var(cpu_hw_events);

	for (idx = 0; idx <= armpmu->num_events; ++idx) {

	for (idx = 0; idx < armpmu->num_events; ++idx) {

		struct perf_event *event = cpuc->events[idx];

		struct hw_perf_event *hwc;
@@ -581,7 +581,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev) 
	perf_sample_data_init(&data, 0);



	cpuc = &__get_cpu_var(cpu_hw_events);

	for (idx = 0; idx <= armpmu->num_events; ++idx) {

	for (idx = 0; idx < armpmu->num_events; ++idx) {

		struct perf_event *event = cpuc->events[idx];

		struct hw_perf_event *hwc;