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Commit d2a160b5 authored by Vivien Didelot's avatar Vivien Didelot Committed by David S. Miller
Browse files

net: dsa: mv88e6xxx: move the Port macros 



Move the PORT_* macros where they belong, in the related port.h header.

Signed-off-by: default avatarVivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c4530ee1

drivers/net/dsa/mv88e6xxx/chip.h

+0 −160
Original line number Diff line number Diff line
@@ -33,166 +33,6 @@ 
#define SMI_CMD_OP_45_READ_DATA_INC	((3 << 10) | SMI_CMD_BUSY)

#define SMI_DATA		0x01



#define PORT_STATUS		0x00

#define PORT_STATUS_PAUSE_EN	BIT(15)

#define PORT_STATUS_MY_PAUSE	BIT(14)

#define PORT_STATUS_HD_FLOW	BIT(13)

#define PORT_STATUS_PHY_DETECT	BIT(12)

#define PORT_STATUS_LINK	BIT(11)

#define PORT_STATUS_DUPLEX	BIT(10)

#define PORT_STATUS_SPEED_MASK	0x0300

#define PORT_STATUS_SPEED_10	0x0000

#define PORT_STATUS_SPEED_100	0x0100

#define PORT_STATUS_SPEED_1000	0x0200

#define PORT_STATUS_EEE		BIT(6) /* 6352 */

#define PORT_STATUS_AM_DIS	BIT(6) /* 6165 */

#define PORT_STATUS_MGMII	BIT(6) /* 6185 */

#define PORT_STATUS_TX_PAUSED	BIT(5)

#define PORT_STATUS_FLOW_CTRL	BIT(4)

#define PORT_STATUS_CMODE_MASK	0x0f

#define PORT_STATUS_CMODE_100BASE_X	0x8

#define PORT_STATUS_CMODE_1000BASE_X	0x9

#define PORT_STATUS_CMODE_SGMII		0xa

#define PORT_STATUS_CMODE_2500BASEX	0xb

#define PORT_STATUS_CMODE_XAUI		0xc

#define PORT_STATUS_CMODE_RXAUI		0xd

#define PORT_PCS_CTRL		0x01

#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK	BIT(15)

#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK	BIT(14)

#define PORT_PCS_CTRL_FORCE_SPEED	BIT(13) /* 6390 */

#define PORT_PCS_CTRL_ALTSPEED		BIT(12) /* 6390 */

#define PORT_PCS_CTRL_200BASE		BIT(12) /* 6352 */

#define PORT_PCS_CTRL_FC		BIT(7)

#define PORT_PCS_CTRL_FORCE_FC		BIT(6)

#define PORT_PCS_CTRL_LINK_UP		BIT(5)

#define PORT_PCS_CTRL_FORCE_LINK	BIT(4)

#define PORT_PCS_CTRL_DUPLEX_FULL	BIT(3)

#define PORT_PCS_CTRL_FORCE_DUPLEX	BIT(2)

#define PORT_PCS_CTRL_SPEED_MASK	(0x03)

#define PORT_PCS_CTRL_SPEED_10		(0x00)

#define PORT_PCS_CTRL_SPEED_100		(0x01)

#define PORT_PCS_CTRL_SPEED_200		(0x02) /* 6065 and non Gb chips */

#define PORT_PCS_CTRL_SPEED_1000	(0x02)

#define PORT_PCS_CTRL_SPEED_10000	(0x03) /* 6390X */

#define PORT_PCS_CTRL_SPEED_UNFORCED	(0x03)

#define PORT_PAUSE_CTRL		0x02

#define PORT_FLOW_CTRL_LIMIT_IN		((0x00 << 8) | BIT(15))

#define PORT_FLOW_CTRL_LIMIT_OUT	((0x01 << 8) | BIT(15))

#define PORT_SWITCH_ID		0x03

#define PORT_SWITCH_ID_PROD_NUM_6085	0x04a

#define PORT_SWITCH_ID_PROD_NUM_6095	0x095

#define PORT_SWITCH_ID_PROD_NUM_6097	0x099

#define PORT_SWITCH_ID_PROD_NUM_6131	0x106

#define PORT_SWITCH_ID_PROD_NUM_6320	0x115

#define PORT_SWITCH_ID_PROD_NUM_6123	0x121

#define PORT_SWITCH_ID_PROD_NUM_6141	0x340

#define PORT_SWITCH_ID_PROD_NUM_6161	0x161

#define PORT_SWITCH_ID_PROD_NUM_6165	0x165

#define PORT_SWITCH_ID_PROD_NUM_6171	0x171

#define PORT_SWITCH_ID_PROD_NUM_6172	0x172

#define PORT_SWITCH_ID_PROD_NUM_6175	0x175

#define PORT_SWITCH_ID_PROD_NUM_6176	0x176

#define PORT_SWITCH_ID_PROD_NUM_6185	0x1a7

#define PORT_SWITCH_ID_PROD_NUM_6190	0x190

#define PORT_SWITCH_ID_PROD_NUM_6190X	0x0a0

#define PORT_SWITCH_ID_PROD_NUM_6191	0x191

#define PORT_SWITCH_ID_PROD_NUM_6240	0x240

#define PORT_SWITCH_ID_PROD_NUM_6290	0x290

#define PORT_SWITCH_ID_PROD_NUM_6321	0x310

#define PORT_SWITCH_ID_PROD_NUM_6341	0x341

#define PORT_SWITCH_ID_PROD_NUM_6352	0x352

#define PORT_SWITCH_ID_PROD_NUM_6350	0x371

#define PORT_SWITCH_ID_PROD_NUM_6351	0x375

#define PORT_SWITCH_ID_PROD_NUM_6390	0x390

#define PORT_SWITCH_ID_PROD_NUM_6390X	0x0a1

#define PORT_CONTROL		0x04

#define PORT_CONTROL_USE_CORE_TAG	BIT(15)

#define PORT_CONTROL_DROP_ON_LOCK	BIT(14)

#define PORT_CONTROL_EGRESS_UNMODIFIED	(0x0 << 12)

#define PORT_CONTROL_EGRESS_UNTAGGED	(0x1 << 12)

#define PORT_CONTROL_EGRESS_TAGGED	(0x2 << 12)

#define PORT_CONTROL_EGRESS_ADD_TAG	(0x3 << 12)

#define PORT_CONTROL_EGRESS_MASK	(0x3 << 12)

#define PORT_CONTROL_HEADER		BIT(11)

#define PORT_CONTROL_IGMP_MLD_SNOOP	BIT(10)

#define PORT_CONTROL_DOUBLE_TAG		BIT(9)

#define PORT_CONTROL_FRAME_MODE_NORMAL		(0x0 << 8)

#define PORT_CONTROL_FRAME_MODE_DSA		(0x1 << 8)

#define PORT_CONTROL_FRAME_MODE_PROVIDER	(0x2 << 8)

#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA	(0x3 << 8)

#define PORT_CONTROL_FRAME_MASK			(0x3 << 8)

#define PORT_CONTROL_DSA_TAG		BIT(8)

#define PORT_CONTROL_VLAN_TUNNEL	BIT(7)

#define PORT_CONTROL_TAG_IF_BOTH	BIT(6)

#define PORT_CONTROL_USE_IP		BIT(5)

#define PORT_CONTROL_USE_TAG		BIT(4)

#define PORT_CONTROL_FORWARD_UNKNOWN	BIT(2)

#define PORT_CONTROL_EGRESS_FLOODS_MASK			(0x3 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA	(0x0 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA	(0x1 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA	(0x2 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA	(0x3 << 2)

#define PORT_CONTROL_STATE_MASK		0x03

#define PORT_CONTROL_STATE_DISABLED	0x00

#define PORT_CONTROL_STATE_BLOCKING	0x01

#define PORT_CONTROL_STATE_LEARNING	0x02

#define PORT_CONTROL_STATE_FORWARDING	0x03

#define PORT_CONTROL_1		0x05

#define PORT_CONTROL_1_MESSAGE_PORT	BIT(15)

#define PORT_CONTROL_1_FID_11_4_MASK	(0xff << 0)

#define PORT_BASE_VLAN		0x06

#define PORT_BASE_VLAN_FID_3_0_MASK	(0xf << 12)

#define PORT_DEFAULT_VLAN	0x07

#define PORT_DEFAULT_VLAN_MASK	0xfff

#define PORT_CONTROL_2		0x08

#define PORT_CONTROL_2_IGNORE_FCS	BIT(15)

#define PORT_CONTROL_2_VTU_PRI_OVERRIDE	BIT(14)

#define PORT_CONTROL_2_SA_PRIO_OVERRIDE	BIT(13)

#define PORT_CONTROL_2_DA_PRIO_OVERRIDE	BIT(12)

#define PORT_CONTROL_2_JUMBO_1522	(0x00 << 12)

#define PORT_CONTROL_2_JUMBO_2048	(0x01 << 12)

#define PORT_CONTROL_2_JUMBO_10240	(0x02 << 12)

#define PORT_CONTROL_2_8021Q_MASK	(0x03 << 10)

#define PORT_CONTROL_2_8021Q_DISABLED	(0x00 << 10)

#define PORT_CONTROL_2_8021Q_FALLBACK	(0x01 << 10)

#define PORT_CONTROL_2_8021Q_CHECK	(0x02 << 10)

#define PORT_CONTROL_2_8021Q_SECURE	(0x03 << 10)

#define PORT_CONTROL_2_DISCARD_TAGGED	BIT(9)

#define PORT_CONTROL_2_DISCARD_UNTAGGED	BIT(8)

#define PORT_CONTROL_2_MAP_DA		BIT(7)

#define PORT_CONTROL_2_DEFAULT_FORWARD	BIT(6)

#define PORT_CONTROL_2_EGRESS_MONITOR	BIT(5)

#define PORT_CONTROL_2_INGRESS_MONITOR	BIT(4)

#define PORT_CONTROL_2_UPSTREAM_MASK	0x0f

#define PORT_RATE_CONTROL	0x09

#define PORT_RATE_CONTROL_2	0x0a

#define PORT_ASSOC_VECTOR	0x0b

#define PORT_ASSOC_VECTOR_HOLD_AT_1		BIT(15)

#define PORT_ASSOC_VECTOR_INT_AGE_OUT		BIT(14)

#define PORT_ASSOC_VECTOR_LOCKED_PORT		BIT(13)

#define PORT_ASSOC_VECTOR_IGNORE_WRONG		BIT(12)

#define PORT_ASSOC_VECTOR_REFRESH_LOCKED	BIT(11)

#define PORT_ATU_CONTROL	0x0c

#define PORT_PRI_OVERRIDE	0x0d

#define PORT_ETH_TYPE		0x0f

#define PORT_ETH_TYPE_DEFAULT	0x9100

#define PORT_IN_DISCARD_LO	0x10

#define PORT_IN_DISCARD_HI	0x11

#define PORT_IN_FILTERED	0x12

#define PORT_OUT_FILTERED	0x13

#define PORT_TAG_REGMAP_0123	0x18

#define PORT_TAG_REGMAP_4567	0x19

#define PORT_IEEE_PRIO_MAP_TABLE	0x18    /* 6390 */

#define PORT_IEEE_PRIO_MAP_TABLE_UPDATE		BIT(15)

#define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP		(0x0 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP	(0x1 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP	(0x2 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP		(0x3 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP	(0x5 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP	(0x6 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP	(0x7 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT		9



#define GLOBAL_STATUS		0x00

#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */

#define GLOBAL_STATUS_PPU_STATE_MASK		(0x3 << 14) /* 6165 6185 */

drivers/net/dsa/mv88e6xxx/port.h

+160 −0
Original line number Diff line number Diff line
@@ -17,6 +17,166 @@ 


#include "chip.h"



#define PORT_STATUS		0x00

#define PORT_STATUS_PAUSE_EN	BIT(15)

#define PORT_STATUS_MY_PAUSE	BIT(14)

#define PORT_STATUS_HD_FLOW	BIT(13)

#define PORT_STATUS_PHY_DETECT	BIT(12)

#define PORT_STATUS_LINK	BIT(11)

#define PORT_STATUS_DUPLEX	BIT(10)

#define PORT_STATUS_SPEED_MASK	0x0300

#define PORT_STATUS_SPEED_10	0x0000

#define PORT_STATUS_SPEED_100	0x0100

#define PORT_STATUS_SPEED_1000	0x0200

#define PORT_STATUS_EEE		BIT(6) /* 6352 */

#define PORT_STATUS_AM_DIS	BIT(6) /* 6165 */

#define PORT_STATUS_MGMII	BIT(6) /* 6185 */

#define PORT_STATUS_TX_PAUSED	BIT(5)

#define PORT_STATUS_FLOW_CTRL	BIT(4)

#define PORT_STATUS_CMODE_MASK	0x0f

#define PORT_STATUS_CMODE_100BASE_X	0x8

#define PORT_STATUS_CMODE_1000BASE_X	0x9

#define PORT_STATUS_CMODE_SGMII		0xa

#define PORT_STATUS_CMODE_2500BASEX	0xb

#define PORT_STATUS_CMODE_XAUI		0xc

#define PORT_STATUS_CMODE_RXAUI		0xd

#define PORT_PCS_CTRL		0x01

#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK	BIT(15)

#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK	BIT(14)

#define PORT_PCS_CTRL_FORCE_SPEED	BIT(13) /* 6390 */

#define PORT_PCS_CTRL_ALTSPEED		BIT(12) /* 6390 */

#define PORT_PCS_CTRL_200BASE		BIT(12) /* 6352 */

#define PORT_PCS_CTRL_FC		BIT(7)

#define PORT_PCS_CTRL_FORCE_FC		BIT(6)

#define PORT_PCS_CTRL_LINK_UP		BIT(5)

#define PORT_PCS_CTRL_FORCE_LINK	BIT(4)

#define PORT_PCS_CTRL_DUPLEX_FULL	BIT(3)

#define PORT_PCS_CTRL_FORCE_DUPLEX	BIT(2)

#define PORT_PCS_CTRL_SPEED_MASK	(0x03)

#define PORT_PCS_CTRL_SPEED_10		(0x00)

#define PORT_PCS_CTRL_SPEED_100		(0x01)

#define PORT_PCS_CTRL_SPEED_200		(0x02) /* 6065 and non Gb chips */

#define PORT_PCS_CTRL_SPEED_1000	(0x02)

#define PORT_PCS_CTRL_SPEED_10000	(0x03) /* 6390X */

#define PORT_PCS_CTRL_SPEED_UNFORCED	(0x03)

#define PORT_PAUSE_CTRL		0x02

#define PORT_FLOW_CTRL_LIMIT_IN		((0x00 << 8) | BIT(15))

#define PORT_FLOW_CTRL_LIMIT_OUT	((0x01 << 8) | BIT(15))

#define PORT_SWITCH_ID		0x03

#define PORT_SWITCH_ID_PROD_NUM_6085	0x04a

#define PORT_SWITCH_ID_PROD_NUM_6095	0x095

#define PORT_SWITCH_ID_PROD_NUM_6097	0x099

#define PORT_SWITCH_ID_PROD_NUM_6131	0x106

#define PORT_SWITCH_ID_PROD_NUM_6320	0x115

#define PORT_SWITCH_ID_PROD_NUM_6123	0x121

#define PORT_SWITCH_ID_PROD_NUM_6141	0x340

#define PORT_SWITCH_ID_PROD_NUM_6161	0x161

#define PORT_SWITCH_ID_PROD_NUM_6165	0x165

#define PORT_SWITCH_ID_PROD_NUM_6171	0x171

#define PORT_SWITCH_ID_PROD_NUM_6172	0x172

#define PORT_SWITCH_ID_PROD_NUM_6175	0x175

#define PORT_SWITCH_ID_PROD_NUM_6176	0x176

#define PORT_SWITCH_ID_PROD_NUM_6185	0x1a7

#define PORT_SWITCH_ID_PROD_NUM_6190	0x190

#define PORT_SWITCH_ID_PROD_NUM_6190X	0x0a0

#define PORT_SWITCH_ID_PROD_NUM_6191	0x191

#define PORT_SWITCH_ID_PROD_NUM_6240	0x240

#define PORT_SWITCH_ID_PROD_NUM_6290	0x290

#define PORT_SWITCH_ID_PROD_NUM_6321	0x310

#define PORT_SWITCH_ID_PROD_NUM_6341	0x341

#define PORT_SWITCH_ID_PROD_NUM_6352	0x352

#define PORT_SWITCH_ID_PROD_NUM_6350	0x371

#define PORT_SWITCH_ID_PROD_NUM_6351	0x375

#define PORT_SWITCH_ID_PROD_NUM_6390	0x390

#define PORT_SWITCH_ID_PROD_NUM_6390X	0x0a1

#define PORT_CONTROL		0x04

#define PORT_CONTROL_USE_CORE_TAG	BIT(15)

#define PORT_CONTROL_DROP_ON_LOCK	BIT(14)

#define PORT_CONTROL_EGRESS_UNMODIFIED	(0x0 << 12)

#define PORT_CONTROL_EGRESS_UNTAGGED	(0x1 << 12)

#define PORT_CONTROL_EGRESS_TAGGED	(0x2 << 12)

#define PORT_CONTROL_EGRESS_ADD_TAG	(0x3 << 12)

#define PORT_CONTROL_EGRESS_MASK	(0x3 << 12)

#define PORT_CONTROL_HEADER		BIT(11)

#define PORT_CONTROL_IGMP_MLD_SNOOP	BIT(10)

#define PORT_CONTROL_DOUBLE_TAG		BIT(9)

#define PORT_CONTROL_FRAME_MODE_NORMAL		(0x0 << 8)

#define PORT_CONTROL_FRAME_MODE_DSA		(0x1 << 8)

#define PORT_CONTROL_FRAME_MODE_PROVIDER	(0x2 << 8)

#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA	(0x3 << 8)

#define PORT_CONTROL_FRAME_MASK			(0x3 << 8)

#define PORT_CONTROL_DSA_TAG		BIT(8)

#define PORT_CONTROL_VLAN_TUNNEL	BIT(7)

#define PORT_CONTROL_TAG_IF_BOTH	BIT(6)

#define PORT_CONTROL_USE_IP		BIT(5)

#define PORT_CONTROL_USE_TAG		BIT(4)

#define PORT_CONTROL_FORWARD_UNKNOWN	BIT(2)

#define PORT_CONTROL_EGRESS_FLOODS_MASK			(0x3 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA	(0x0 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA	(0x1 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA	(0x2 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA	(0x3 << 2)

#define PORT_CONTROL_STATE_MASK		0x03

#define PORT_CONTROL_STATE_DISABLED	0x00

#define PORT_CONTROL_STATE_BLOCKING	0x01

#define PORT_CONTROL_STATE_LEARNING	0x02

#define PORT_CONTROL_STATE_FORWARDING	0x03

#define PORT_CONTROL_1		0x05

#define PORT_CONTROL_1_MESSAGE_PORT	BIT(15)

#define PORT_CONTROL_1_FID_11_4_MASK	(0xff << 0)

#define PORT_BASE_VLAN		0x06

#define PORT_BASE_VLAN_FID_3_0_MASK	(0xf << 12)

#define PORT_DEFAULT_VLAN	0x07

#define PORT_DEFAULT_VLAN_MASK	0xfff

#define PORT_CONTROL_2		0x08

#define PORT_CONTROL_2_IGNORE_FCS	BIT(15)

#define PORT_CONTROL_2_VTU_PRI_OVERRIDE	BIT(14)

#define PORT_CONTROL_2_SA_PRIO_OVERRIDE	BIT(13)

#define PORT_CONTROL_2_DA_PRIO_OVERRIDE	BIT(12)

#define PORT_CONTROL_2_JUMBO_1522	(0x00 << 12)

#define PORT_CONTROL_2_JUMBO_2048	(0x01 << 12)

#define PORT_CONTROL_2_JUMBO_10240	(0x02 << 12)

#define PORT_CONTROL_2_8021Q_MASK	(0x03 << 10)

#define PORT_CONTROL_2_8021Q_DISABLED	(0x00 << 10)

#define PORT_CONTROL_2_8021Q_FALLBACK	(0x01 << 10)

#define PORT_CONTROL_2_8021Q_CHECK	(0x02 << 10)

#define PORT_CONTROL_2_8021Q_SECURE	(0x03 << 10)

#define PORT_CONTROL_2_DISCARD_TAGGED	BIT(9)

#define PORT_CONTROL_2_DISCARD_UNTAGGED	BIT(8)

#define PORT_CONTROL_2_MAP_DA		BIT(7)

#define PORT_CONTROL_2_DEFAULT_FORWARD	BIT(6)

#define PORT_CONTROL_2_EGRESS_MONITOR	BIT(5)

#define PORT_CONTROL_2_INGRESS_MONITOR	BIT(4)

#define PORT_CONTROL_2_UPSTREAM_MASK	0x0f

#define PORT_RATE_CONTROL	0x09

#define PORT_RATE_CONTROL_2	0x0a

#define PORT_ASSOC_VECTOR	0x0b

#define PORT_ASSOC_VECTOR_HOLD_AT_1		BIT(15)

#define PORT_ASSOC_VECTOR_INT_AGE_OUT		BIT(14)

#define PORT_ASSOC_VECTOR_LOCKED_PORT		BIT(13)

#define PORT_ASSOC_VECTOR_IGNORE_WRONG		BIT(12)

#define PORT_ASSOC_VECTOR_REFRESH_LOCKED	BIT(11)

#define PORT_ATU_CONTROL	0x0c

#define PORT_PRI_OVERRIDE	0x0d

#define PORT_ETH_TYPE		0x0f

#define PORT_ETH_TYPE_DEFAULT	0x9100

#define PORT_IN_DISCARD_LO	0x10

#define PORT_IN_DISCARD_HI	0x11

#define PORT_IN_FILTERED	0x12

#define PORT_OUT_FILTERED	0x13

#define PORT_TAG_REGMAP_0123	0x18

#define PORT_TAG_REGMAP_4567	0x19

#define PORT_IEEE_PRIO_MAP_TABLE	0x18    /* 6390 */

#define PORT_IEEE_PRIO_MAP_TABLE_UPDATE		BIT(15)

#define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP		(0x0 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP	(0x1 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP	(0x2 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP		(0x3 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP	(0x5 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP	(0x6 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP	(0x7 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT		9



int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,

			u16 *val);

int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,