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Commit d299e4b6 authored by prudhvi Yarlagadda's avatar prudhvi Yarlagadda Committed by Prudhvi Yarlagadda
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ARM: dts: msm: Add SSC QUPV3 DT nodes for SM8150 



Add device tree nodes for SSC QUPV3 serial engines
to support spi protocol.

Change-Id: I0ec6812ad9b6f257ae5083870345e29bcb87d62e
Signed-off-by: default avatarprudhvi Yarlagadda <pyarlaga@codeaurora.org>
parent f7d9441c

arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi

+38 −0
Original line number Diff line number Diff line
@@ -1035,4 +1035,42 @@ 
		status = "disabled";

	};



	/* SPI */

	qupv3_se21_spi: spi@2684000 {

		compatible = "qcom,spi-geni";

		reg = <0x2684000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 443 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se21_spi_active>;

		pinctrl-1 = <&qupv3_se21_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_3>;

		status = "disabled";

	};



	qupv3_se22_spi: spi@2688000 {

		compatible = "qcom,spi-geni";

		reg = <0x2688000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 444 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,

			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se22_spi_active>;

		pinctrl-1 = <&qupv3_se22_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_3>;

		status = "disabled";

	};

};

arch/arm64/boot/dts/qcom/sm8150-slpi-pinctrl.dtsi

+66 −0
Original line number Diff line number Diff line
@@ -128,5 +128,71 @@ 
				};

			};

		};



		/* SE21 pin mappings */

		qupv3_se21_spi_pins: qupv3_se21_spi_pins {

			qupv3_se21_spi_active: qupv3_se21_spi_active {

				mux {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					function = "func1";

				};



				config {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se21_spi_sleep: qupv3_se21_spi_sleep {

				mux {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					function = "gpio";

				};



				config {

					pins = "gpio2", "gpio3", "gpio4",

								"gpio5";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		/*SE22 pin mappings*/

		qupv3_se22_spi_pins: qupv3_se22_spi_pins {

			qupv3_se22_spi_active: qupv3_se22_spi_active {

				mux {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					function = "func1";

				};



				config {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se22_spi_sleep: qupv3_se22_spi_sleep {

				mux {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					function = "gpio";

				};



				config {

					pins = "gpio6", "gpio7", "gpio8",

								"gpio9";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};

	};

};