Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d23f3839 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tony Lindgren
Browse files

ARM: dts: DRA7: Add pcie1 dt node for EP mode 



Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 5e452865

arch/arm/boot/dts/am571x-idk.dts

+9 −0
Original line number Diff line number Diff line
@@ -96,3 +96,12 @@ 
		status = "okay";

	};

};



&pcie1_rc {

	status = "okay";

	gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;

};



&pcie1_ep {

	gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;

};

arch/arm/boot/dts/am572x-idk.dts

+6 −1
Original line number Diff line number Diff line
@@ -88,7 +88,12 @@ 
	load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;

};



&pcie1 {

&pcie1_rc {

	status = "okay";

	gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;

};



&pcie1_ep {

	gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;

};

arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -570,7 +570,12 @@ 
	};

};



&pcie1 {

&pcie1_rc {

	status = "ok";

	gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;

};



&pcie1_ep {

	gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;

};

arch/arm/boot/dts/dra7-evm.dts

+4 −0
Original line number Diff line number Diff line
@@ -729,3 +729,7 @@ 
		status = "okay";

	};

};



&pcie1_rc {

	status = "okay";

};

arch/arm/boot/dts/dra7.dtsi

+22 −1
Original line number Diff line number Diff line
@@ -196,6 +196,7 @@ 
				scm_conf1: scm_conf@1c04 {

					compatible = "syscon";

					reg = <0x1c04 0x0020>;

					#syscon-cells = <2>;

				};



				scm_conf_pcie: scm_conf@1c24 {
@@ -287,7 +288,11 @@ 
			#address-cells = <1>;

			ranges = <0x51000000 0x51000000 0x3000

				  0x0	     0x20000000 0x10000000>;

			pcie1: pcie@51000000 {

			/**

			 * To enable PCI endpoint mode, disable the pcie1_rc

			 * node and enable pcie1_ep mode.

			 */

			pcie1_rc: pcie@51000000 {

				compatible = "ti,dra7-pcie";

				reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;

				reg-names = "rc_dbics", "ti_conf", "config";
@@ -309,12 +314,28 @@ 
						<0 0 0 2 &pcie1_intc 2>,

						<0 0 0 3 &pcie1_intc 3>,

						<0 0 0 4 &pcie1_intc 4>;

				status = "disabled";

				pcie1_intc: interrupt-controller {

					interrupt-controller;

					#address-cells = <0>;

					#interrupt-cells = <1>;

				};

			};



			pcie1_ep: pcie_ep@51000000 {

				compatible = "ti,dra7-pcie-ep";

				reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;

				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";

				interrupts = <0 232 0x4>;

				num-lanes = <1>;

				num-ib-windows = <4>;

				num-ob-windows = <16>;

				ti,hwmods = "pcie1";

				phys = <&pcie1_phy>;

				phy-names = "pcie-phy0";

				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;

				status = "disabled";

			};

		};



		axi@1 {