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Commit d236b7b0 authored by David Collins's avatar David Collins
Browse files

ARM: dts: msm: use VDD_CX, VDD_MX, VDD_MMCX regulator phandles on SDMSHRIKE 



Switch the regulator supply phandles used for VDD_CX, VDD_MX, and
VDD_MMCX so that device tree configurations are clearer.

Change-Id: I198b272dda19285ad6b6fd9af43b0711639002e2
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent 6ab58e3d

arch/arm64/boot/dts/qcom/sdmshrike-regulators.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -278,8 +278,8 @@ 
		compatible = "qcom,rpmh-arc-regulator";

		mboxes = <&apps_rsc 0>;

		qcom,resource-name = "cx.lvl";

		pm855_2_s3_level-parent-supply = <&pm855p_s3_level>;

		pm855_2_s3_level_ao-parent-supply = <&pm855p_s3_level_ao>;

		pm855_2_s3_level-parent-supply = <&VDD_MX_LEVEL>;

		pm855_2_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>;



		VDD_CX_LEVEL: S3E_LEVEL:

		pm855_2_s3_level: regulator-pm855_2-s3-level {

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+19 −19
Original line number Diff line number Diff line
@@ -482,9 +482,9 @@ 
		compatible = "qcom,gcc-sdmshrike";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855_2_s3_level>;

		vdd_cx_ao-supply = <&pm855_2_s3_level_ao>;

		vdd_mm-supply = <&pm855p_s1_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -493,7 +493,7 @@ 
		compatible = "qcom,npucc-sdm855";

		reg = <0x9910000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855_2_s3_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_gdsc-supply = <&npu_core_gdsc>;

		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -503,7 +503,7 @@ 
		compatible = "qcom,dispcc-sdm855";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855p_s1_level>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;

		#clock-cells = <1>;
@@ -524,8 +524,8 @@ 
		compatible = "qcom,gpucc-sdmshrike";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855_2_s3_level>;

		vdd_mx-supply = <&pm855p_s3_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -636,7 +636,7 @@ 
&bps_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -644,7 +644,7 @@ 
&ipe_0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -652,7 +652,7 @@ 
&ipe_1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -660,7 +660,7 @@ 
&ife_0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -668,7 +668,7 @@ 
&ife_1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -676,7 +676,7 @@ 
&ife_2_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -684,7 +684,7 @@ 
&ife_3_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -692,7 +692,7 @@ 
&titan_top_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -700,7 +700,7 @@ 
&mdss_core_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_DISP_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -718,7 +718,7 @@ 
&mvsc_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -726,7 +726,7 @@ 
&mvs0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -734,7 +734,7 @@ 
&mvs1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

	parent-supply = <&pm855p_s1_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};