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Commit d1fa08f3 authored by Patrik Jakobsson's avatar Patrik Jakobsson
Browse files

drm/gma500: Make all chips use gma_wait_for_vblank 



Also remove the duplicated oaktrail function.

Signed-off-by: default avatarPatrik Jakobsson <patrik.r.jakobsson@gmail.com>
parent ad3c46ea

drivers/gpu/drm/gma500/cdv_intel_dp.c

+2 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include "psb_drv.h"

#include "psb_intel_drv.h"

#include "psb_intel_reg.h"

#include "gma_display.h"

#include <drm/drm_dp_helper.h>



#define _wait_for(COND, MS, W) ({ \
@@ -1317,7 +1318,7 @@ cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder) 
	/* Enable output, wait for it to become active */

	REG_WRITE(intel_dp->output_reg, reg);

	REG_READ(intel_dp->output_reg);

	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	DRM_DEBUG_KMS("Link config\n");

	/* Write the link configuration data */

drivers/gpu/drm/gma500/mdfld_intel_display.c

+3 −3
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe) 
	}



	/* FIXME JLIU7_PO */

	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);

	return;



	/* Wait for for the pipe disable to take effect. */
@@ -93,7 +93,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe) 
	}



	/* FIXME JLIU7_PO */

	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);

	return;



	/* Wait for for the pipe enable to take effect. */
@@ -1034,7 +1034,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, 


	/* Wait for for the pipe enable to take effect. */

	REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);

	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



mrst_crtc_mode_set_exit:

drivers/gpu/drm/gma500/oaktrail_crtc.c

+3 −3
Original line number Diff line number Diff line
@@ -242,7 +242,7 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) 
			REG_READ(map->conf);

		}

		/* Wait for for the pipe disable to take effect. */

		psb_intel_wait_for_vblank(dev);

		gma_wait_for_vblank(dev);



		temp = REG_READ(map->dpll);

		if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -484,10 +484,10 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, 


	REG_WRITE(map->conf, pipeconf);

	REG_READ(map->conf);

	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	REG_WRITE(map->cntr, dspcntr);

	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



oaktrail_crtc_mode_set_exit:

	gma_power_end(dev);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

+3 −9
Original line number Diff line number Diff line
@@ -155,12 +155,6 @@ static void oaktrail_hdmi_audio_disable(struct drm_device *dev) 
	HDMI_READ(HDMI_HCR);

}



static void wait_for_vblank(struct drm_device *dev)

{

	/* Wait for 20ms, i.e. one cycle at 50hz. */

	mdelay(20);

}



static unsigned int htotal_calculate(struct drm_display_mode *mode)

{

	u32 htotal, new_crtc_htotal;
@@ -372,10 +366,10 @@ int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, 


	REG_WRITE(PCH_PIPEBCONF, pipeconf);

	REG_READ(PCH_PIPEBCONF);

	wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	REG_WRITE(dspcntr_reg, dspcntr);

	wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	gma_power_end(dev);
@@ -459,7 +453,7 @@ void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode) 
			REG_READ(PCH_PIPEBCONF);

		}



		wait_for_vblank(dev);

		gma_wait_for_vblank(dev);



		/* Enable plane */

		temp = REG_READ(DSPBCNTR);

drivers/gpu/drm/gma500/psb_intel_display.c

+5 −11
Original line number Diff line number Diff line
@@ -82,12 +82,6 @@ static void psb_intel_clock(int refclk, struct gma_clock_t *clock) 
	clock->dot = clock->vco / clock->p;

}



void psb_intel_wait_for_vblank(struct drm_device *dev)

{

	/* Wait for 20ms, i.e. one cycle at 50hz. */

	mdelay(20);

}



static int psb_intel_pipe_set_base(struct drm_crtc *crtc,

			    int x, int y, struct drm_framebuffer *old_fb)

{
@@ -244,7 +238,7 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) 
		}



		/* Wait for vblank for the disable to take effect. */

		psb_intel_wait_for_vblank(dev);

		gma_wait_for_vblank(dev);



		temp = REG_READ(map->dpll);

		if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -516,14 +510,14 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 
	REG_WRITE(map->conf, pipeconf);

	REG_READ(map->conf);



	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	REG_WRITE(map->cntr, dspcntr);



	/* Flush the plane changes */

	crtc_funcs->mode_set_base(crtc, x, y, old_fb);



	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	return 0;

}
@@ -669,12 +663,12 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc) 
	REG_WRITE(map->base, crtc_state->saveDSPBASE);

	REG_WRITE(map->conf, crtc_state->savePIPECONF);



	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);

	REG_WRITE(map->base, crtc_state->saveDSPBASE);



	psb_intel_wait_for_vblank(dev);

	gma_wait_for_vblank(dev);



	paletteReg = map->palette;

	for (i = 0; i < 256; ++i)