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Commit d1ae25a0 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Fix ASPM workaround usage 



The PCIE Workaround register (AR_WA/0x4004) is used to handle
various hardware quirks. For AR9002 chips, AR_WA_D3_L1_DISABLE
is used to prevent the HW from automatically entering L1 state
when D3 is enforced.

AR_WA_D3_L1_DISABLE has to be enabled for a few AR9280 based
cards, mark them based on their PCI subdevice/subvendor IDs
and enforce it in ar9002_hw_configpcipowersave().

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 8aada63c

drivers/net/wireless/ath/ath9k/ar9002_hw.c

+11 −18
Original line number Diff line number Diff line
@@ -269,12 +269,11 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, 
			if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)

				val |= AR_WA_D3_L1_DISABLE;

		} else {

			if (((AR_SREV_9285(ah) ||

			      AR_SREV_9271(ah) ||

			      AR_SREV_9287(ah)) &&

			     (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||

			    (AR_SREV_9280(ah) &&

			     (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {

			if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) {

				if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)

					val |= AR_WA_D3_L1_DISABLE;

			} else if (AR_SREV_9280(ah)) {

				if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE)

					val |= AR_WA_D3_L1_DISABLE;

			}

		}
@@ -297,23 +296,17 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, 
	} else {

		if (ah->config.pcie_waen) {

			val = ah->config.pcie_waen;

			if (!power_off)

			val &= (~AR_WA_D3_L1_DISABLE);

		} else {

			if (AR_SREV_9285(ah) ||

			    AR_SREV_9271(ah) ||

			    AR_SREV_9287(ah)) {

			if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) {

				val = AR9285_WA_DEFAULT;

				if (!power_off)

				val &= (~AR_WA_D3_L1_DISABLE);

			}

			else if (AR_SREV_9280(ah)) {

			} else if (AR_SREV_9280(ah)) {

				/*

				 * For AR9280 chips, bit 22 of 0x4004

				 * needs to be set.

				 */

				val = AR9280_WA_DEFAULT;

				if (!power_off)

				val &= (~AR_WA_D3_L1_DISABLE);

			} else {

				val = AR_WA_DEFAULT;

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+1 −6
Original line number Diff line number Diff line
@@ -763,11 +763,6 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah, 
	if (!power_off /* !restore */) {

		/* set bit 19 to allow forcing of pcie core into L1 state */

		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);



		/* Several PCIe massages to ensure proper behaviour */

		if (ah->config.pcie_waen)

			REG_WRITE(ah, AR_WA, ah->config.pcie_waen);

		else

		REG_WRITE(ah, AR_WA, ah->WARegVal);

	}

drivers/net/wireless/ath/ath9k/ath9k.h

+1 −0
Original line number Diff line number Diff line
@@ -631,6 +631,7 @@ void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 
#define ATH9K_PCI_CUS217     0x0004

#define ATH9K_PCI_WOW        0x0008

#define ATH9K_PCI_BT_ANT_DIV 0x0010

#define ATH9K_PCI_D3_L1_WAR  0x0020



/*

 * Default cache line size, in bytes.

drivers/net/wireless/ath/ath9k/hw.c

+0 −1
Original line number Diff line number Diff line
@@ -450,7 +450,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah) 
	ah->config.ack_6mb = 0x0;

	ah->config.cwm_ignore_extcca = 0;

	ah->config.pcie_clock_req = 0;

	ah->config.pcie_waen = 0;

	ah->config.analog_shiftreg = 1;



	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {

drivers/net/wireless/ath/ath9k/init.c

+5 −0
Original line number Diff line number Diff line
@@ -551,6 +551,11 @@ static void ath9k_init_platform(struct ath_softc *sc) 
		pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;

		ath_info(common, "Set BT/WLAN RX diversity capability\n");

	}



	if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {

		ah->config.pcie_waen = 0x0040473b;

		ath_info(common, "Enable WAR for ASPM D3/L1\n");

	}

}



static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,