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Commit d1a559a1 authored by Heiko Stübner's avatar Heiko Stübner Committed by Mike Turquette
Browse files

clk: rockchip: add missing rk3288 npll rate table 



The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Tested-by: default avatarDoug Anderson <dianders@chromium.org>
Tested-by: default avatarKever Yang <kever.yang@rock-chips.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent f9c0d140

drivers/clk/rockchip/clk-rk3288.c

+1 −1
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { 
	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),

		     RK3288_MODE_CON, 12, 8, rk3288_pll_rates),

	[npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),

		     RK3288_MODE_CON, 14, 9, NULL),

		     RK3288_MODE_CON, 14, 9, rk3288_pll_rates),

};



static struct clk_div_table div_hclk_cpu_t[] = {