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Commit d173c910 authored by Ramachandran Venkataramani's avatar Ramachandran Venkataramani
Browse files

clk: qcom: Add clkref enable for PCIe and USB clkrefs 



Add clkref enables required by the PCIe and
sde_dp phy drivers.

Change-Id: I329ec36f6abfa5729b62493c2df5a280b3a2bb9d
Signed-off-by: default avatarRamachandran Venkataramani <ramavenk@codeaurora.org>
parent 8d0fbc83

drivers/clk/qcom/gcc-sdmshrike.c

+56 −0
Original line number Diff line number Diff line
@@ -2662,6 +2662,19 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 
	},

};



static struct clk_branch gcc_pcie_0_clkref_clk = {

	.halt_reg = 0x8c00c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c00c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_pcie_0_mstr_axi_clk = {

	.halt_reg = 0x6b018,

	.halt_check = BRANCH_HALT_VOTED,
@@ -2749,6 +2762,19 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 
	},

};



static struct clk_branch gcc_pcie_1_clkref_clk = {

	.halt_reg = 0x8c02c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c02c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_pcie_1_mstr_axi_clk = {

	.halt_reg = 0x8d018,

	.halt_check = BRANCH_HALT_VOTED,
@@ -4524,6 +4550,19 @@ static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 
	},

};



static struct clk_branch gcc_usb3_prim_clkref_clk = {

	.halt_reg = 0x8c008,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c008,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_usb3_prim_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_usb3_prim_phy_aux_clk = {

	.halt_reg = 0xf050,

	.halt_check = BRANCH_HALT,
@@ -4572,6 +4611,19 @@ static struct clk_gate2 gcc_usb3_prim_phy_pipe_clk = { 
	},

};



static struct clk_branch gcc_usb3_sec_clkref_clk = {

	.halt_reg = 0x8c028,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c028,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_usb3_sec_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_usb3_sec_phy_aux_clk = {

	.halt_reg = 0x10050,

	.halt_check = BRANCH_HALT,
@@ -4757,6 +4809,7 @@ static struct clk_regmap *gcc_sdmshrike_clocks[] = { 
	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,

	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,

	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,

	[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,

	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,

	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,

	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
@@ -4764,6 +4817,7 @@ static struct clk_regmap *gcc_sdmshrike_clocks[] = { 
	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,

	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,

	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,

	[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,

	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,

	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,

	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
@@ -4932,10 +4986,12 @@ static struct clk_regmap *gcc_sdmshrike_clocks[] = { 
	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,

	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,

	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,

	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,

	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,

	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,

	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,

	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,

	[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,

	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,

	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,

	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,

include/dt-bindings/clock/qcom,gcc-sdmshrike.h

+4 −0
Original line number Diff line number Diff line
@@ -257,6 +257,10 @@ 
#define GPLL1							240

#define GPLL4							241

#define GPLL7							242

#define GCC_PCIE_0_CLKREF_CLK					243

#define GCC_PCIE_1_CLKREF_CLK					244

#define GCC_USB3_PRIM_CLKREF_CLK				245

#define GCC_USB3_SEC_CLKREF_CLK					246



#define GCC_EMAC_BCR						0

#define GCC_GPU_BCR							1