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Commit d152b220 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: qcom: qcs405: Add cfg_offset for blsp1_uart3 clock 



The CFG/M/N/D registers are at an offset of 0x20 from the CMD register for
blsp1_uart3 clock, so add the same.

Change-Id: I42c27b36b79a8e1031cbf163f96833e490aaf685
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent a60934ca

drivers/clk/qcom/gcc-qcs405.c

+1 −0
Original line number Diff line number Diff line
@@ -743,6 +743,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 
	.cmd_rcgr = 0x4014,

	.mnd_width = 16,

	.hid_width = 5,

	.cfg_off = 0x20,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,

	.clkr.hw.init = &(struct clk_init_data){