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Commit d150cef4 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
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MIPS: Netlogic: XLP9XX PIC updates 



Functions for the XLP9XX interrupt table entry format and other PIC
register changes.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6279/
parent 5513c760

arch/mips/include/asm/netlogic/xlp-hal/pic.h

+48 −24
Original line number Diff line number Diff line
@@ -150,12 +150,19 @@ 
#define PIC_IRT0		0x74

#define PIC_IRT(i)		(PIC_IRT0 + ((i) * 2))



#define TIMER_CYCLES_MAXVAL	0xffffffffffffffffULL

#define PIC_9XX_PENDING_0	0x6

#define PIC_9XX_PENDING_1	0x8

#define PIC_9XX_PENDING_2	0xa

#define PIC_9XX_PENDING_3	0xc



#define PIC_9XX_IRT0		0x1c0

#define PIC_9XX_IRT(i)		(PIC_9XX_IRT0 + ((i) * 2))



/*

 *    IRT Map

 */

#define PIC_NUM_IRTS		160

#define PIC_9XX_NUM_IRTS	256



#define PIC_IRT_WD_0_INDEX	0

#define PIC_IRT_WD_1_INDEX	1
@@ -205,30 +212,26 @@ 


#define nlm_read_pic_reg(b, r)	nlm_read_reg64(b, r)

#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)

#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))

#define nlm_get_pic_pcibase(node)	nlm_pcicfg_base(cpu_is_xlp9xx() ? \

		XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))

#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)



/* We use PIC on node 0 as a timer */

#define pic_timer_freq()		nlm_get_pic_frequency(0)



/* IRT and h/w interrupt routines */

static inline int

nlm_pic_read_irt(uint64_t base, int irt_index)

{

	return nlm_read_pic_reg(base, PIC_IRT(irt_index));

}



static inline void

nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)

nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,

	int sch, int vec, int dt, int db, int cpu)

{

	uint64_t val;



	val = nlm_read_pic_reg(base, PIC_IRT(irt));

	/* clear cpuset and mask */

	val &= ~((0x7ull << 16) | 0xffff);

	/* set DB, cpuset and cpumask */

	val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));

	nlm_write_pic_reg(base, PIC_IRT(irt), val);

	val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |

			((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |

			((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |

			(cpu & 0x3ff);



	nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);

}



static inline void
@@ -249,6 +252,10 @@ static inline void 
nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,

	int sch, int vec, int cpu)

{

	if (cpu_is_xlp9xx())

		nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,

							1, 0, cpu);

	else

		nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,

			(cpu >> 4),		/* thread group */

			1 << (cpu & 0xf));	/* thread mask */
@@ -293,17 +300,29 @@ nlm_pic_enable_irt(uint64_t base, int irt) 
{

	uint64_t reg;



	if (cpu_is_xlp9xx()) {

		reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));

		nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));

	} else {

		reg = nlm_read_pic_reg(base, PIC_IRT(irt));

		nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));

	}

}



static inline void

nlm_pic_disable_irt(uint64_t base, int irt)

{

	uint64_t reg;



	if (cpu_is_xlp9xx()) {

		reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));

		reg &= ~((uint64_t)1 << 22);

		nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);

	} else {

		reg = nlm_read_pic_reg(base, PIC_IRT(irt));

	nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));

		reg &= ~((uint64_t)1 << 31);

		nlm_write_pic_reg(base, PIC_IRT(irt), reg);

	}

}



static inline void
@@ -311,8 +330,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) 
{

	uint64_t ipi;



	ipi = ((uint64_t)nmi << 31) | (irq << 20);

	ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */

	if (cpu_is_xlp9xx())

		ipi = (nmi << 23) | (irq << 24) |

			(0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;

	else

		ipi = ((uint64_t)nmi << 31) | (irq << 20) |

			((hwt >> 4) << 16) | (1 << (hwt & 0xf));



	nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);

}

arch/mips/netlogic/xlp/nlm_hal.c

+15 −0
Original line number Diff line number Diff line
@@ -69,6 +69,17 @@ int nlm_irq_to_irt(int irq) 
	uint64_t pcibase;

	int devoff, irt;



	/* bypass for 9xx */

	if (cpu_is_xlp9xx()) {

		switch (irq) {

		case PIC_UART_0_IRQ:

			return 133;

		case PIC_UART_1_IRQ:

			return 134;

		}

		return -1;

	}



	devoff = 0;

	switch (irq) {

	case PIC_UART_0_IRQ:
@@ -277,6 +288,10 @@ static unsigned int nlm_2xx_get_pic_frequency(int node) 


unsigned int nlm_get_pic_frequency(int node)

{

	/* TODO Has to calculate freq as like 2xx */

	if (cpu_is_xlp9xx())

		return 250000000;



	if (cpu_is_xlpii())

		return nlm_2xx_get_pic_frequency(node);

	else

arch/mips/netlogic/xlp/wakeup.c

+1 −1
Original line number Diff line number Diff line
@@ -47,8 +47,8 @@ 
#include <asm/netlogic/mips-extns.h>



#include <asm/netlogic/xlp-hal/iomap.h>

#include <asm/netlogic/xlp-hal/pic.h>

#include <asm/netlogic/xlp-hal/xlp.h>

#include <asm/netlogic/xlp-hal/pic.h>

#include <asm/netlogic/xlp-hal/sys.h>



static int xlp_wakeup_core(uint64_t sysbase, int node, int core)

arch/mips/pci/pci-xlp.c

+1 −1
Original line number Diff line number Diff line
@@ -50,8 +50,8 @@ 
#include <asm/netlogic/mips-extns.h>



#include <asm/netlogic/xlp-hal/iomap.h>

#include <asm/netlogic/xlp-hal/pic.h>

#include <asm/netlogic/xlp-hal/xlp.h>

#include <asm/netlogic/xlp-hal/pic.h>

#include <asm/netlogic/xlp-hal/pcibus.h>

#include <asm/netlogic/xlp-hal/bridge.h>