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Commit d13d4e06 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks 



The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.

Fixes: bcde3722 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 91a7c50c

arch/arm/boot/dts/r8a7790.dtsi

+5 −2
Original line number Original line Diff line number Diff line
@@ -1443,8 +1443,11 @@ 
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;

			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;

			clocks = <&p_clk>,

			clocks = <&p_clk>,

				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,

				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,

				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,

				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,

				<&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,

				<&p_clk>,

				<&p_clk>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,