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Commit d1371f8c authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu: change pcie_gen_cap magic code to macro 



This patch changes pcie_gen_cap magic code to macro to make it more
readable.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Cc: Eric Huang <JinHuiEric.Huang@amd.com>
Cc: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4d54588e

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+0 −3
Original line number Diff line number Diff line
@@ -1978,9 +1978,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) 
	return r;

}



#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2, asic 1/2/3 */

#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */



void amdgpu_get_pcie_info(struct amdgpu_device *adev)

{

	u32 mask;

drivers/gpu/drm/amd/include/amd_pcie.h

+14 −0
Original line number Diff line number Diff line
@@ -37,6 +37,13 @@ 
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF

#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0



/* gen: chipset 1/2, asic 1/2/3 */

#define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \

				      | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \

				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \

				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \

				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)



/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */

#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000

#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
@@ -47,4 +54,11 @@ 
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000

#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16



/* 1/2/4/8/16 lanes */

#define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \

				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \

				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \

				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \

				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)



#endif

drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c

+2 −2
Original line number Diff line number Diff line
@@ -733,7 +733,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;

		result = cgs_query_system_info(hwmgr->device, &sys_info);

		if (result)

			data->pcie_gen_cap = 0x30007;

			data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;

		else

			data->pcie_gen_cap = (uint32_t)sys_info.value;

		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
@@ -742,7 +742,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;

		result = cgs_query_system_info(hwmgr->device, &sys_info);

		if (result)

			data->pcie_lane_cap = 0x2f0000;

			data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;

		else

			data->pcie_lane_cap = (uint32_t)sys_info.value;

	} else {

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

+2 −2
Original line number Diff line number Diff line
@@ -3293,7 +3293,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;

		result = cgs_query_system_info(hwmgr->device, &sys_info);

		if (result)

			data->pcie_gen_cap = 0x30007;

			data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;

		else

			data->pcie_gen_cap = (uint32_t)sys_info.value;

		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
@@ -3302,7 +3302,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;

		result = cgs_query_system_info(hwmgr->device, &sys_info);

		if (result)

			data->pcie_lane_cap = 0x2f0000;

			data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;

		else

			data->pcie_lane_cap = (uint32_t)sys_info.value;

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c

+2 −2
Original line number Diff line number Diff line
@@ -4638,7 +4638,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;

		result = cgs_query_system_info(hwmgr->device, &sys_info);

		if (result)

			data->pcie_gen_cap = 0x30007;

			data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;

		else

			data->pcie_gen_cap = (uint32_t)sys_info.value;

		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
@@ -4647,7 +4647,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;

		result = cgs_query_system_info(hwmgr->device, &sys_info);

		if (result)

			data->pcie_lane_cap = 0x2f0000;

			data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;

		else

			data->pcie_lane_cap = (uint32_t)sys_info.value;

	} else {