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Commit d07ed23f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next 

Pull Samsung clk updates from Sylwester Nawrocki:

 - addition of the CPU clock configuration data for Exynos4412
   Prime SoC variant,
 - removal of driver for deprecated Exynos4415 SoC,
 - switching from the syscore to regular system sleep PM ops
   in the audio subsystem clocks controller driver,
 - updates of the definitions of some "Network On Chip" related
   clocks.

* tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung:
  clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)
  clk: samsung: exynos-audss: Replace syscore PM with platform device PM
  clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical
  clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
parents f4a0a6c3 cb4ac949

Documentation/devicetree/bindings/clock/exynos4415-clock.txt

deleted100644 → 0
+0 −38
Original line number Diff line number Diff line 
* Samsung Exynos4415 Clock Controller



The Exynos4415 clock controller generates and supplies clock to various

consumer devices within the Exynos4415 SoC.



Required properties:



- compatible: should be one of the following:

  - "samsung,exynos4415-cmu" - for the main system clocks controller

    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).

  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory

    Controller (DMC) domain clock controller.



- reg: physical base address of the controller and length of memory mapped

  region.



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume.



All available clocks are defined as preprocessor macros in

dt-bindings/clock/exynos4415.h header and can be used in device

tree sources.



Example 1: An example of a clock controller node is listed below.



	cmu: clock-controller@10030000 {

		compatible = "samsung,exynos4415-cmu";

		reg = <0x10030000 0x18000>;

		#clock-cells = <1>;

	};



	cmu-dmc: clock-controller@105C0000 {

		compatible = "samsung,exynos4415-cmu-dmc";

		reg = <0x105C0000 0x3000>;

		#clock-cells = <1>;

	};

drivers/clk/samsung/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -5,7 +5,6 @@ 
obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o clk-cpu.o

obj-$(CONFIG_SOC_EXYNOS3250)	+= clk-exynos3250.o

obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o

obj-$(CONFIG_SOC_EXYNOS4415)	+= clk-exynos4415.o

obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o

obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o

obj-$(CONFIG_SOC_EXYNOS5410)	+= clk-exynos5410.o

drivers/clk/samsung/clk-exynos-audss.c

+10 −14
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ static unsigned long reg_save[][2] = { 
	{ ASS_CLK_GATE, 0 },

};



static int exynos_audss_clk_suspend(void)

static int exynos_audss_clk_suspend(struct device *dev)

{

	int i;
@@ -54,18 +54,15 @@ static int exynos_audss_clk_suspend(void) 
	return 0;

}



static void exynos_audss_clk_resume(void)

static int exynos_audss_clk_resume(struct device *dev)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(reg_save); i++)

		writel(reg_save[i][1], reg_base + reg_save[i][0]);

}



static struct syscore_ops exynos_audss_clk_syscore_ops = {

	.suspend	= exynos_audss_clk_suspend,

	.resume		= exynos_audss_clk_resume,

};

	return 0;

}

#endif /* CONFIG_PM_SLEEP */



struct exynos_audss_clk_drvdata {
@@ -251,9 +248,6 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) 
		goto unregister;

	}



#ifdef CONFIG_PM_SLEEP

	register_syscore_ops(&exynos_audss_clk_syscore_ops);

#endif

	return 0;



unregister:
@@ -267,10 +261,6 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) 


static int exynos_audss_clk_remove(struct platform_device *pdev)

{

#ifdef CONFIG_PM_SLEEP

	unregister_syscore_ops(&exynos_audss_clk_syscore_ops);

#endif



	of_clk_del_provider(pdev->dev.of_node);



	exynos_audss_clk_teardown();
@@ -281,10 +271,16 @@ static int exynos_audss_clk_remove(struct platform_device *pdev) 
	return 0;

}



static const struct dev_pm_ops exynos_audss_clk_pm_ops = {

	SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_audss_clk_suspend,

				     exynos_audss_clk_resume)

};



static struct platform_driver exynos_audss_clk_driver = {

	.driver	= {

		.name = "exynos-audss-clk",

		.of_match_table = exynos_audss_clk_of_match,

		.pm = &exynos_audss_clk_pm_ops,

	},

	.probe = exynos_audss_clk_probe,

	.remove = exynos_audss_clk_remove,

drivers/clk/samsung/clk-exynos4.c

+4 −0
Original line number Diff line number Diff line
@@ -1298,6 +1298,8 @@ static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = 
};



static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {

	PLL_35XX_RATE(1704000000, 213, 3, 0),

	PLL_35XX_RATE(1600000000, 200, 3, 0),

	PLL_35XX_RATE(1500000000, 250, 4, 0),

	PLL_35XX_RATE(1400000000, 175, 3, 0),

	PLL_35XX_RATE(1300000000, 325, 6, 0),
@@ -1421,6 +1423,8 @@ static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { 
		(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))



static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {

	{ 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },

	{ 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },

	{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },

	{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },

	{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },