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Commit d05fddd3 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update GPUCC clock controller for SDM855"

parents 7a73fabd f6adf52a

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

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Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding

--------------------------------------------------------------------



Required properties :

- compatible : shall contain :

		"qcom,gpucc-sdm855"



- reg : shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

		Must contain "cc_base".

- #clock-cells : shall contain 1.

- #reset-cells : shall contain 1.

- vdd_cx-supply : The vdd_cx logic rail supply.

- vdd_mx-supply : The vdd_mx logic rail supply.



Optional properties :

- #power-domain-cells : shall contain 1.



Example:

	clock_gpucc: qcom,gpucc {

		compatible = "qcom,gpucc-sdm855";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_mx-supply = <&pm855l_s4_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+5 −5
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@@ -839,8 +839,11 @@ 
	};



	clock_gpucc: qcom,gpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		compatible = "qcom,gpucc-sdm855";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_mx-supply = <&pm855l_s4_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -2216,9 +2219,6 @@ 
&gpu_gx_gdsc {

	parent-supply = <&pm855l_s2_level>;

	qcom,vote-parent-supply-voltage;

	clock-names = "core_root_clk";

	clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>;

	qcom,force-enable-root-clk;

	status = "ok";

};

arch/arm64/configs/sdm855-perf_defconfig

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@@ -370,6 +370,7 @@ CONFIG_CLOCK_CPU_OSM=y 
CONFIG_MSM_DISPCC_SDM855=y

CONFIG_MSM_DEBUGCC_SDM855=y

CONFIG_MSM_CLK_RPMH=y

CONFIG_MSM_GPUCC_SDM855=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y

arch/arm64/configs/sdm855_defconfig

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@@ -381,6 +381,7 @@ CONFIG_CLOCK_CPU_OSM=y 
CONFIG_MSM_DISPCC_SDM855=y

CONFIG_MSM_DEBUGCC_SDM855=y

CONFIG_MSM_CLK_RPMH=y

CONFIG_MSM_GPUCC_SDM855=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_QCOM_APCS_IPC=y

drivers/clk/qcom/Kconfig

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@@ -289,3 +289,11 @@ config MSM_CLK_RPMH 
	  SoCs. It accepts requests from other hardware subsystems via RSC.

	  Say Y to support the clocks managed by RPMh VRM/ARC on platforms

	  such as sdm845.



config MSM_GPUCC_SDM855

	tristate "SDM855 Graphics Clock Controller"

	depends on MSM_GCC_SDM855

	help

	  Support for the graphics clock controller on Qualcomm Technologies, Inc.

	  sdm855 devices.

	  Say Y if you want to support graphics controller devices.