Loading drivers/clk/qcom/camcc-sm8150.c +1 −1 Original line number Diff line number Diff line Loading @@ -38,7 +38,7 @@ #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner); enum { Loading drivers/clk/qcom/dispcc-sm8150.c +1 −1 Original line number Diff line number Diff line Loading @@ -38,7 +38,7 @@ #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner); #define DISP_CC_MISC_CMD 0x8000 Loading drivers/clk/qcom/gcc-sm8150.c +1 −1 Original line number Diff line number Diff line Loading @@ -43,7 +43,7 @@ static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner); enum { P_AUD_REF_CLK, Loading drivers/clk/qcom/npucc-sm8150.c +13 −5 Original line number Diff line number Diff line Loading @@ -111,11 +111,14 @@ static const struct alpha_pll_config npu_cc_pll0_config = { }; static const struct alpha_pll_config npu_cc_pll0_config_sm8150_v2 = { .l = 0xD, .alpha = 0x555, .l = 0x1F, .alpha = 0x4000, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002267, .config_ctl_hi1_val = 0x00000024, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000000, .test_ctl_hi1_val = 0x00000020, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000805, .user_ctl_hi1_val = 0x000000D0, Loading Loading @@ -186,6 +189,9 @@ static const struct alpha_pll_config npu_cc_pll1_config_sm8150_v2 = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002267, .config_ctl_hi1_val = 0x00000024, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000000, .test_ctl_hi1_val = 0x00000020, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000805, .user_ctl_hi1_val = 0x000000D0, Loading Loading @@ -255,7 +261,8 @@ static const struct freq_tbl ftbl_npu_cc_cal_dp_clk_src_sm8150_v2[] = { F(300000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(400000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(487000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(773000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(652000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(811000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(908000000, P_NPU_CC_CRC_DIV, 1, 0, 0), { } }; Loading Loading @@ -662,8 +669,9 @@ static void npu_cc_sm8150_fixup_sm8150v2(struct regmap *regmap) npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_MIN] = 0; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 400000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] = 487000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 773000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 908000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 652000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 811000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_HIGH_L1] = 908000000; npu_cc_npu_core_clk_src.freq_tbl = ftbl_npu_cc_npu_core_clk_src_sm8150_v2; npu_cc_npu_core_clk_src.clkr.hw.init->rate_max[VDD_MIN] = 0; Loading drivers/clk/qcom/vdd-level.h +4 −1 Original line number Diff line number Diff line /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -25,6 +25,8 @@ enum vdd_levels { VDD_LOW_L1, /* SVSL1 */ VDD_NOMINAL, /* NOM */ VDD_HIGH, /* TURBO */ VDD_HIGH_L1, /* TURBOL1 */ VDD_MM_NUM = VDD_HIGH_L1, VDD_NUM, }; Loading @@ -36,6 +38,7 @@ static int vdd_corner[] = { RPMH_REGULATOR_LEVEL_SVS_L1, /* VDD_LOW_L1 */ RPMH_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */ RPMH_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */ RPMH_REGULATOR_LEVEL_TURBO_L1, /* VDD_HIGH_L1 */ }; #endif Loading
drivers/clk/qcom/camcc-sm8150.c +1 −1 Original line number Diff line number Diff line Loading @@ -38,7 +38,7 @@ #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner); enum { Loading
drivers/clk/qcom/dispcc-sm8150.c +1 −1 Original line number Diff line number Diff line Loading @@ -38,7 +38,7 @@ #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner); #define DISP_CC_MISC_CMD 0x8000 Loading
drivers/clk/qcom/gcc-sm8150.c +1 −1 Original line number Diff line number Diff line Loading @@ -43,7 +43,7 @@ static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner); enum { P_AUD_REF_CLK, Loading
drivers/clk/qcom/npucc-sm8150.c +13 −5 Original line number Diff line number Diff line Loading @@ -111,11 +111,14 @@ static const struct alpha_pll_config npu_cc_pll0_config = { }; static const struct alpha_pll_config npu_cc_pll0_config_sm8150_v2 = { .l = 0xD, .alpha = 0x555, .l = 0x1F, .alpha = 0x4000, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002267, .config_ctl_hi1_val = 0x00000024, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000000, .test_ctl_hi1_val = 0x00000020, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000805, .user_ctl_hi1_val = 0x000000D0, Loading Loading @@ -186,6 +189,9 @@ static const struct alpha_pll_config npu_cc_pll1_config_sm8150_v2 = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002267, .config_ctl_hi1_val = 0x00000024, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000000, .test_ctl_hi1_val = 0x00000020, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000805, .user_ctl_hi1_val = 0x000000D0, Loading Loading @@ -255,7 +261,8 @@ static const struct freq_tbl ftbl_npu_cc_cal_dp_clk_src_sm8150_v2[] = { F(300000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(400000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(487000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(773000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(652000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(811000000, P_NPU_CC_CRC_DIV, 1, 0, 0), F(908000000, P_NPU_CC_CRC_DIV, 1, 0, 0), { } }; Loading Loading @@ -662,8 +669,9 @@ static void npu_cc_sm8150_fixup_sm8150v2(struct regmap *regmap) npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_MIN] = 0; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 400000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] = 487000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 773000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 908000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 652000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 811000000; npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_HIGH_L1] = 908000000; npu_cc_npu_core_clk_src.freq_tbl = ftbl_npu_cc_npu_core_clk_src_sm8150_v2; npu_cc_npu_core_clk_src.clkr.hw.init->rate_max[VDD_MIN] = 0; Loading
drivers/clk/qcom/vdd-level.h +4 −1 Original line number Diff line number Diff line /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -25,6 +25,8 @@ enum vdd_levels { VDD_LOW_L1, /* SVSL1 */ VDD_NOMINAL, /* NOM */ VDD_HIGH, /* TURBO */ VDD_HIGH_L1, /* TURBOL1 */ VDD_MM_NUM = VDD_HIGH_L1, VDD_NUM, }; Loading @@ -36,6 +38,7 @@ static int vdd_corner[] = { RPMH_REGULATOR_LEVEL_SVS_L1, /* VDD_LOW_L1 */ RPMH_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */ RPMH_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */ RPMH_REGULATOR_LEVEL_TURBO_L1, /* VDD_HIGH_L1 */ }; #endif