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Commit d0011f29 authored by Isaac J. Manjarres's avatar Isaac J. Manjarres
Browse files

ARM: dts: msm: Add support for proper TLB and Cache Sizes 



Add L2 TLB, L1 instruction cache, and L1 data cache sizes
for all the CPU cores supported on the sdm855.

Change-Id: I3b1df04a5cab63beb5de839affb1a3dd9a7bd401
Signed-off-by: default avatarIsaac J. Manjarres <isaacm@codeaurora.org>
parent 90e4b68f

arch/arm64/boot/dts/qcom/sdm855.dtsi

+32 −32
Original line number Diff line number Diff line
@@ -74,16 +74,16 @@ 


			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x8800>;

			};



			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x9000>;

			};



			L1_TLB_0: l1-tlb {

				qcom,dump-size = <0x3000>;

				qcom,dump-size = <0x5000>;

			};

		};
@@ -106,16 +106,16 @@ 


			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x8800>;

			};



			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x9000>;

			};



			L1_TLB_100: l1-tlb {

				qcom,dump-size = <0x3000>;

				qcom,dump-size = <0x5000>;

			};

		};
@@ -138,16 +138,16 @@ 


			L1_I_200: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x8800>;

			};



			L1_D_200: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x9000>;

			};



			L1_TLB_200: l1-tlb {

				qcom,dump-size = <0x3000>;

				qcom,dump-size = <0x5000>;

			};

		};
@@ -170,16 +170,16 @@ 


			L1_I_300: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x8800>;

			};



			L1_D_300: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

				qcom,dump-size = <0x9000>;

			};



			L1_TLB_300: l1-tlb {

				qcom,dump-size = <0x3000>;

				qcom,dump-size = <0x5000>;

			};

		};
@@ -202,16 +202,16 @@ 


			L1_I_400: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x11000>;

			};



			L1_D_400: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x12000>;

			};



			L1_TLB_400: l1-tlb {

				qcom,dump-size = <0x3c00>;

				qcom,dump-size = <0x7800>;

			};

		};
@@ -234,16 +234,16 @@ 


			L1_I_500: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x11000>;

			};



			L1_D_500: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x12000>;

			};



			L1_TLB_500: l1-tlb {

				qcom,dump-size = <0x3c00>;

				qcom,dump-size = <0x7800>;

			};

		};
@@ -266,16 +266,16 @@ 


			L1_I_600: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x11000>;

			};



			L1_D_600: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x12000>;

			};



			L1_TLB_600: l1-tlb {

				qcom,dump-size = <0x3c00>;

				qcom,dump-size = <0x7800>;

			};

		};
@@ -298,16 +298,16 @@ 


			L1_I_700: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x11000>;

			};



			L1_D_700: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

				qcom,dump-size = <0x12000>;

			};



			L1_TLB_700: l1-tlb {

				qcom,dump-size = <0x3c00>;

				qcom,dump-size = <0x7800>;

			};

		};
@@ -1838,42 +1838,42 @@ 


		qcom,l1_tlb_dump0 {

			qcom,dump-node = <&L1_TLB_0>;

			qcom,dump-id = <0x20>;

			qcom,dump-id = <0x120>;

		};



		qcom,l1_tlb_dump100 {

			qcom,dump-node = <&L1_TLB_100>;

			qcom,dump-id = <0x21>;

			qcom,dump-id = <0x121>;

		};



		qcom,l1_tlb_dump200 {

			qcom,dump-node = <&L1_TLB_200>;

			qcom,dump-id = <0x22>;

			qcom,dump-id = <0x122>;

		};



		qcom,l1_tlb_dump300 {

			qcom,dump-node = <&L1_TLB_300>;

			qcom,dump-id = <0x23>;

			qcom,dump-id = <0x123>;

		};



		qcom,l1_tlb_dump400 {

			qcom,dump-node = <&L1_TLB_400>;

			qcom,dump-id = <0x24>;

			qcom,dump-id = <0x124>;

		};



		qcom,l1_tlb_dump500 {

			qcom,dump-node = <&L1_TLB_500>;

			qcom,dump-id = <0x25>;

			qcom,dump-id = <0x125>;

		};



		qcom,l1_tlb_dump600 {

			qcom,dump-node = <&L1_TLB_600>;

			qcom,dump-id = <0x26>;

			qcom,dump-id = <0x126>;

		};



		qcom,l1_tlb_dump700 {

			qcom,dump-node = <&L1_TLB_700>;

			qcom,dump-id = <0x27>;

			qcom,dump-id = <0x127>;

		};

	};