Commit cf719012 authored Apr 05, 2017 by Chen-Yu Tsai Committed by Maxime Ripard Apr 05, 2017

clk: sunxi-ng: mult: Support PLL lock detection

Some PLL clocks are N (multiplier) type clocks, or can be simplified
as such. An example of the former is the DDR1 PLL clock on the A33.
An example of the latter is the CPU PLL clock on the A80, in which
the P divider is only used for low frequencies that are of little
use. Both clocks support PLL lock detection.

The mult clock macro implies support for this, but that is not true.
The field is simply discarded. This patch adds proper support for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent cdb8b80b

drivers/clk/sunxi-ng/ccu_mult.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -137,6 +137,8 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,

		spin_unlock_irqrestore(cm->common.lock, flags);

		ccu_helper_wait_for_lock(&cm->common, cm->lock);

		return 0;
		}

drivers/clk/sunxi-ng/ccu_mult.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -33,6 +33,7 @@ struct ccu_mult_internal {

		struct ccu_mult {
		u32 enable;
		u32 lock;

		struct ccu_frac_internal frac;
		struct ccu_mult_internal mult;
		@@ -45,6 +46,7 @@ struct ccu_mult {
		_flags) \
		struct ccu_mult _struct = { \
		.enable = _gate, \
		.lock = _lock, \
		.mult = _SUNXI_CCU_MULT(_mshift, _mwidth), \
		.common = { \
		.reg = _reg, \