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Commit cee29012 authored by Ghanim Fodi's avatar Ghanim Fodi Committed by Gerrit - the friendly Code Review server
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msm: ipa4: Adapt IPA resource groups for IPA 4.5 



Add support for the new group, QDSS.
Adapt the resource groups to their new numbers.
Configure different min/max resource limits per
resource group that are appropriate for IPA4.5.

CRs-fixed: 2268613
Change-Id: I560218d7dbd2eb5c67802a13e5789f7dad6a6ae2
Signed-off-by: default avatarGhanim Fodi <gfodi@codeaurora.org>
parent b8f54403

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+119 −27
Original line number Diff line number Diff line
@@ -147,6 +147,17 @@ 
#define IPA_v4_2_GROUP_UL_DL		(0)

#define IPA_v4_2_SRC_GROUP_MAX		(1)

#define IPA_v4_2_DST_GROUP_MAX		(1)



#define IPA_v4_5_MHI_GROUP_PCIE		(0)

#define IPA_v4_5_ETHERNET		(0)

#define IPA_v4_5_GROUP_UL_DL		(1)

#define IPA_v4_5_MHI_GROUP_DDR		(1)

#define IPA_v4_5_MHI_GROUP_DMA		(2)

#define IPA_v4_5_MHI_GROUP_QDSS		(3)

#define IPA_v4_5_GROUP_UC_RX_Q		(4)

#define IPA_v4_5_SRC_GROUP_MAX		(5)

#define IPA_v4_5_DST_GROUP_MAX		(5)



#define IPA_GROUP_MAX IPA_v3_0_GROUP_MAX



enum ipa_rsrc_grp_type_src {
@@ -334,7 +345,34 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {

		{5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},



	[IPA_4_5] = {

		/* not used  UL_DL  not used  not used  UC_RX_Q

		 * other are invalid

		 */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{0, 0}, {1, 63}, {0, 0}, {0, 0}, {1, 63}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {

		{0, 0}, {14, 14}, {0, 0}, {0, 0}, {3, 3}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {

		{0, 0}, {18, 18}, {0, 0}, {0, 0}, {8, 8}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {

		{0, 0}, {0, 63}, {0, 0}, {0, 0},  {0, 63}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {

		{0, 0}, {24, 24}, {0, 0}, {0, 0}, {8, 8}, {0, 0} },

	},

	[IPA_4_5_MHI] = {

		/* PCIE  DDR  DMA  QDSS  not used  other are invalid */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{3, 8}, {4, 11}, {1, 1}, {1, 1}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {

		{9, 9}, {12, 12}, {2, 2}, {2, 2}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {

		{9, 9}, {14, 14}, {4, 4}, {4, 4}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {

		{0, 63}, {0, 63}, {0, 63}, {0, 63},  {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {

		{22, 22}, {16, 16}, {6, 6}, {2, 2}, {0, 0}, {0, 0} },

	},

};



static const struct rsrc_min_max ipa3_rsrc_dst_grp_config
@@ -397,6 +435,20 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config 
		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{1, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5] = {

		/* ETH  UL/DL/DPL  not used   not used  uC  other are invalid */

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {

		{16, 16}, {5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{2, 63}, {1, 63}, {0, 0}, {0, 0}, {0, 2}, {0, 0} },

	},

	[IPA_4_5_MHI] = {

		/* PCIE/DPL  DDR  DMA  QDSS  uC  other are invalid */

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {

		{16, 16}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{2, 63}, {1, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} },

	},

};



static const struct rsrc_min_max ipa3_rsrc_rx_grp_config
@@ -441,6 +493,18 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config 
		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{4, 4}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5] = {

		/* not used  UL_DL  not used  not used  UC_RX_Q

		 * other are invalid

		 */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{0, 0}, {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5_MHI] = {

		/* PCIE  DDR  DMA  QDSS  not used  other are invalid */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{ 3, 3 }, {3, 3}, {3, 3}, {3, 3}, {0, 0}, { 0, 0 } },

	},



};
@@ -474,10 +538,6 @@ static const u32 ipa3_rsrc_rx_grp_hps_weight_config 
		/* LWA_DL UL_DL	not used UC_RX_Q, other are invalid */

		[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 },

	},

	[IPA_4_2] = {

		/* UL_DL, other are invalid */

		[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 0, 0, 0, 0, 0 },

	},

};



enum ipa_ees {
@@ -5458,11 +5518,23 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index, 
	case IPA_4_5_MHI:

		if (src) {

			switch (group_index) {

			case IPA_v4_2_GROUP_UL_DL:

			case IPA_v4_5_MHI_GROUP_PCIE:

			case IPA_v4_5_GROUP_UL_DL:

				ipahal_write_reg_n_fields(

					IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n,

					n, val);

				break;

			case IPA_v4_5_MHI_GROUP_DMA:

			case IPA_v4_5_MHI_GROUP_QDSS:

				ipahal_write_reg_n_fields(

					IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n,

					n, val);

				break;

			case IPA_v4_5_GROUP_UC_RX_Q:

				ipahal_write_reg_n_fields(

					IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n,

					n, val);

				break;

			default:

				IPAERR(

				" Invalid source resource group,index #%d\n",
@@ -5471,11 +5543,23 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index, 
			}

		} else {

			switch (group_index) {

			case IPA_v4_2_GROUP_UL_DL:

			case IPA_v4_5_MHI_GROUP_PCIE:

			case IPA_v4_5_GROUP_UL_DL:

				ipahal_write_reg_n_fields(

					IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,

					n, val);

				break;

			case IPA_v4_5_MHI_GROUP_DMA:

			case IPA_v4_5_MHI_GROUP_QDSS:

				ipahal_write_reg_n_fields(

					IPA_DST_RSRC_GRP_23_RSRC_TYPE_n,

					n, val);

				break;

			case IPA_v4_5_GROUP_UC_RX_Q:

				ipahal_write_reg_n_fields(

					IPA_DST_RSRC_GRP_45_RSRC_TYPE_n,

					n, val);

				break;

			default:

				IPAERR(

				" Invalid destination resource group,index #%d\n",
@@ -5492,7 +5576,8 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index, 
	}

}



static void ipa3_configure_rx_hps_clients(int depth, bool min)

static void ipa3_configure_rx_hps_clients(int depth,

	int max_clnt_in_depth, int base_index, bool min)

{

	int i;

	struct ipahal_reg_rx_hps_clients val;
@@ -5500,23 +5585,19 @@ static void ipa3_configure_rx_hps_clients(int depth, bool min) 


	hw_type_idx = ipa3_get_hw_type_index();



	/*

	 * depth 0 contains 4 first clients out of 6

	 * depth 1 contains 2 last clients out of 6

	 */

	for (i = 0 ; i < (depth ? 2 : 4) ; i++) {

	for (i = 0 ; i < max_clnt_in_depth ; i++) {

		if (min)

			val.client_minmax[i] =

				ipa3_rsrc_rx_grp_config

				[hw_type_idx]

				[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ]

				[!depth ? i : 4 + i].min;

				[i + base_index].min;

		else

			val.client_minmax[i] =

				ipa3_rsrc_rx_grp_config

				[hw_type_idx]

				[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ]

				[!depth ? i : 4 + i].max;

				[i + base_index].max;

	}

	if (depth) {

		ipahal_write_reg_fields(min ? IPA_RX_HPS_CLIENTS_MIN_DEPTH_1 :
@@ -5566,9 +5647,9 @@ void ipa3_set_resorce_groups_min_max_limits(void) 
	int dst_grp_idx_max;

	struct ipahal_reg_rsrc_grp_cfg val;

	u8 hw_type_idx;

	int rx_hps_max_clnt_in_depth0;



	IPADBG("ENTER\n");

	IPADBG("Assign source rsrc groups min-max limits\n");



	hw_type_idx = ipa3_get_hw_type_index();

	switch (hw_type_idx) {
@@ -5604,8 +5685,8 @@ void ipa3_set_resorce_groups_min_max_limits(void) 
	case IPA_4_5_MHI:

		src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX;

		dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX;

		src_grp_idx_max = IPA_v4_2_SRC_GROUP_MAX;

		dst_grp_idx_max = IPA_v4_2_DST_GROUP_MAX;

		src_grp_idx_max = IPA_v4_5_SRC_GROUP_MAX;

		dst_grp_idx_max = IPA_v4_5_DST_GROUP_MAX;

		break;

	default:

		IPAERR("invalid hw type index\n");
@@ -5613,6 +5694,7 @@ void ipa3_set_resorce_groups_min_max_limits(void) 
		return;

	}



	IPADBG("Assign source rsrc groups min-max limits\n");

	for (i = 0; i < src_rsrc_type_max; i++) {

		for (j = 0; j < src_grp_idx_max; j = j + 2) {

			val.x_min =
@@ -5628,7 +5710,6 @@ void ipa3_set_resorce_groups_min_max_limits(void) 
	}



	IPADBG("Assign destination rsrc groups min-max limits\n");



	for (i = 0; i < dst_rsrc_type_max; i++) {

		for (j = 0; j < dst_grp_idx_max; j = j + 2) {

			val.x_min =
@@ -5643,7 +5724,7 @@ void ipa3_set_resorce_groups_min_max_limits(void) 
		}

	}



	/* move resource group configuration from HLOS to TZ */

	/* move rx_hps resource group configuration from HLOS to TZ */

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_1) {

		IPAERR("skip configuring ipa_rx_hps_clients from HLOS\n");

		return;
@@ -5651,18 +5732,29 @@ void ipa3_set_resorce_groups_min_max_limits(void) 


	IPADBG("Assign RX_HPS CMDQ rsrc groups min-max limits\n");



	ipa3_configure_rx_hps_clients(0, true);

	ipa3_configure_rx_hps_clients(0, false);

	/* Starting IPA4.5 have 5 RX_HPS_CMDQ */

	if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5)

		rx_hps_max_clnt_in_depth0 = 4;

	else

		rx_hps_max_clnt_in_depth0 = 5;



	/* only hw_type v3_0\3_1 have 6 RX_HPS_CMDQ and needs depth 1*/

	ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, true);

	ipa3_configure_rx_hps_clients(0, rx_hps_max_clnt_in_depth0, 0, false);



	/*

	 * IPA 3.0/3.1 uses 6 RX_HPS_CMDQ and needs depths1 for that

	 * which has two clients

	 */

	if (ipa3_ctx->ipa_hw_type <= IPA_HW_v3_1) {

		ipa3_configure_rx_hps_clients(1, true);

		ipa3_configure_rx_hps_clients(1, false);

		ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0,

			true);

		ipa3_configure_rx_hps_clients(1, 2, rx_hps_max_clnt_in_depth0,

			false);

	}



	/* In IPA4.2 no support to HPS weight config*/

	/* Starting IPA4.2 no support to HPS weight config */

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5 &&

		(ipa3_ctx->ipa_hw_type != IPA_HW_v4_2))

		(ipa3_ctx->ipa_hw_type < IPA_HW_v4_2))

		ipa3_configure_rx_hps_weight();



	IPADBG("EXIT\n");

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+83 −0
Original line number Diff line number Diff line
@@ -213,6 +213,33 @@ static void ipareg_construct_rx_hps_clients_depth0_v3_5( 
		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(3));

}



static void ipareg_construct_rx_hps_clients_depth0_v4_5(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{

	struct ipahal_reg_rx_hps_clients *clients =

		(struct ipahal_reg_rx_hps_clients *)fields;



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[0],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_SHFT_v4_5,

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[1],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_SHFT_v4_5,

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[2],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_SHFT_v4_5,

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[3],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_SHFT_v4_5,

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[4],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_SHFT_v4_5,

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_BMSK_v4_5);

}



static void ipareg_construct_rsrg_grp_xy(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{
@@ -258,6 +285,32 @@ static void ipareg_construct_rsrg_grp_xy_v3_5( 
		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5);

}



static void ipareg_construct_rsrg_grp_xy_v4_5(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{

	struct ipahal_reg_rsrc_grp_cfg *grp =

		(struct ipahal_reg_rsrc_grp_cfg *)fields;



	IPA_SETFIELD_IN_REG(*val, grp->x_min,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5);

	IPA_SETFIELD_IN_REG(*val, grp->x_max,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5);



	/* SRC_45 and DST_45 register has only X fields at ipa V4_5 */

	if (reg == IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n ||

		reg == IPA_DST_RSRC_GRP_45_RSRC_TYPE_n)

		return;



	IPA_SETFIELD_IN_REG(*val, grp->y_min,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5);

	IPA_SETFIELD_IN_REG(*val, grp->y_max,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5);

}



static void ipareg_construct_hash_cfg_n(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{
@@ -2271,6 +2324,8 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
	[IPA_HW_v4_0][IPA_ENDP_YELLOW_RED_MARKER] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00000CC0, 0x70, 10, 23, 1},



	/* IPA4.2 */

	[IPA_HW_v4_2][IPA_IDLE_INDICATION_CFG] = {

		ipareg_construct_idle_indication_cfg, ipareg_parse_dummy,

		0x00000240, 0, 0, 0, 0},
@@ -2278,6 +2333,34 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
		ipareg_construct_endp_init_hol_block_timer_n_v4_2,

		ipareg_parse_dummy,

		0x00000830, 0x70, 8, 17, 1},



	/* IPA4.5 */

	[IPA_HW_v4_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy,

		0x00000400, 0x20, 0, 0, 0},

	[IPA_HW_v4_5][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy,

		0x00000404, 0x20, 0, 0, 0},

	[IPA_HW_v4_5][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy,

		0x00000408, 0x20, 0, 0, 0},

	[IPA_HW_v4_5][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy,

		0x00000500, 0x20, 0, 0, 0},

	[IPA_HW_v4_5][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy,

		0x00000504, 0x20, 0, 0, 0},

	[IPA_HW_v4_5][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v4_5, ipareg_parse_dummy,

		0x00000508, 0x20, 0, 0, 0},

	[IPA_HW_v4_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = {

		ipareg_construct_rx_hps_clients_depth0_v4_5,

		ipareg_parse_dummy,

		0x000023c4, 0, 0, 0, 0},

	[IPA_HW_v4_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = {

		ipareg_construct_rx_hps_clients_depth0_v4_5,

		ipareg_parse_dummy,

		0x000023cc, 0, 0, 0, 0},

};



void ipahal_print_all_regs(bool print_to_dmesg)

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

+3 −3
Original line number Diff line number Diff line
@@ -368,7 +368,7 @@ struct ipahal_reg_debug_cnt_ctrl { 
};



/*

 * struct ipahal_reg_rsrc_grp_cfg - Mix/Max values for two rsrc groups

 * struct ipahal_reg_rsrc_grp_cfg - Min/Max values for two rsrc groups

 * @x_min - first group min value

 * @x_max - first group max value

 * @y_min - second group min value
@@ -383,11 +383,11 @@ struct ipahal_reg_rsrc_grp_cfg { 


/*

 * struct ipahal_reg_rx_hps_clients - Min or Max values for RX HPS clients

 * @client_minmax - Min or Max values. In case of depth 0 the 4 values

 * @client_minmax - Min or Max values. In case of depth 0 the 4 or 5 values

 *	are used. In case of depth 1, only the first 2 values are used

 */

struct ipahal_reg_rx_hps_clients {

	u32 client_minmax[4];

	u32 client_minmax[5];

};



/*

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h

+11 −1
Original line number Diff line number Diff line
@@ -365,11 +365,21 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5 0x3F

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5 0



/* IPA_IPA_IPA_RX_HPS_CLIENTS_MIN/MAX_DEPTH_0/1 registers */

/* IPA_RX_HPS_CLIENTS_MIN/MAX_DEPTH_0/1 registers */

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(n) (0x7F << (8 * (n)))

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(n) \

						(0xF << (8 * (n)))

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(n) (8 * (n))

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_BMSK_v4_5 0xF0000000

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_4_SHFT_v4_5 28

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_BMSK_v4_5 0xF000000

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_3_SHFT_v4_5 24

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_BMSK_v4_5 0xF0000

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_2_SHFT_v4_5 16

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_BMSK_v4_5 0xF00

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_1_SHFT_v4_5 8

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_BMSK_v4_5 0xF

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_0_CLIENT_0_SHFT_v4_5 0



/* IPA_QSB_MAX_WRITES register */

#define IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK (0xf)