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Commit ceac26c6 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Jason Cooper
Browse files

clk: mvebu: armada-375: Fix the description of the SAR in the comment 



For dealing with the code we use the SAR1 and not the SAR0. The code
was correct, and now the comments too.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: default avatarLeigh Brown <leigh@solinno.co.uk>
Link: https://lkml.kernel.org/r/1409645719-20003-5-git-send-email-gregory.clement@free-electrons.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 5e1a63f5

drivers/clk/mvebu/armada-375.c

+2 −2
Original line number Diff line number Diff line
@@ -27,14 +27,14 @@ 
 * all modified at the same time, and not separately as for the Armada

 * 370 or the Armada XP SoCs.

 *

 * SAR0[21:17]   : CPU frequency    DDR frequency   L2 frequency

 * SAR1[21:17]   : CPU frequency    DDR frequency   L2 frequency

 *		 6   =  400 MHz	    400 MHz	    200 MHz

 *		 15  =  600 MHz	    600 MHz	    300 MHz

 *		 21  =  800 MHz	    534 MHz	    400 MHz

 *		 25  = 1000 MHz	    500 MHz	    500 MHz

 *		 others reserved.

 *

 * SAR0[22]   : TCLK frequency

 * SAR1[22]   : TCLK frequency

 *		 0 = 166 MHz

 *		 1 = 200 MHz

 */