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Commit ce84c7c6 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mv88e6390-batch-three' 



Andrew Lunn says:

====================
mv88e6390 batch 3

More patches to support the MV88e6390. This is mostly refactoring
existing code and adding implementations for the mv88e6390.  This
patchset set which reserved frames are sent to the cpu, the size of
jumbo frames that will be accepted, turn off egress rate limiting, and
configuration of pause frames.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 7a6c5cb9 3ce0e65e

drivers/net/dsa/mv88e6xxx/chip.c

+102 −23
Original line number Diff line number Diff line
@@ -2582,10 +2582,6 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
	    mv88e6xxx_6185_family(chip))

		reg = PORT_CONTROL_2_MAP_DA;



	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||

	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))

		reg |= PORT_CONTROL_2_JUMBO_10240;



	if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {

		/* Set the upstream port this port should use */

		reg |= dsa_upstream_port(ds);
@@ -2604,6 +2600,12 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
			return err;

	}



	if (chip->info->ops->port_jumbo_config) {

		err = chip->info->ops->port_jumbo_config(chip, port);

		if (err)

			return err;

	}



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and
@@ -2623,17 +2625,15 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
	if (err)

		return err;



	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||

	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||

	    mv88e6xxx_6320_family(chip)) {

		/* Do not limit the period of time that this port can

		 * be paused for by the remote end or the period of

		 * time that this port can pause the remote end.

		 */

		err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);

	if (chip->info->ops->port_pause_config) {

		err = chip->info->ops->port_pause_config(chip, port);

		if (err)

			return err;

	}



	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||

	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||

	    mv88e6xxx_6320_family(chip)) {

		/* Port ATU control: disable limiting the number of

		 * address database entries that this port is allowed

		 * to use.
@@ -2655,17 +2655,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
			return err;

	}



	/* Rate Control: disable ingress rate limiting. */

	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||

	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||

	    mv88e6xxx_6320_family(chip)) {

		err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,

					   0x0001);

		if (err)

			return err;

	} else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {

		err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,

					   0x0000);

	if (chip->info->ops->port_egress_rate_limiting) {

		err = chip->info->ops->port_egress_rate_limiting(chip, port);

		if (err)

			return err;

	}
@@ -2899,6 +2890,17 @@ static int mv88e6xxx_setup(struct dsa_switch *ds) 
			goto unlock;

	}



	/* Some generations have the configuration of sending reserved

	 * management frames to the CPU in global2, others in

	 * global1. Hence it does not fit the two setup functions

	 * above.

	 */

	if (chip->info->ops->mgmt_rsvd2cpu) {

		err = chip->info->ops->mgmt_rsvd2cpu(chip);

		if (err)

			goto unlock;

	}



unlock:

	mutex_unlock(&chip->reg_lock);
@@ -3215,12 +3217,15 @@ static const struct mv88e6xxx_ops mv88e6085_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6095_ops = {
@@ -3237,6 +3242,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = { 
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6097_ops = {
@@ -3251,12 +3257,16 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6123_ops = {
@@ -3275,6 +3285,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops = { 
	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6131_ops = {
@@ -3289,12 +3300,16 @@ static const struct mv88e6xxx_ops mv88e6131_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6161_ops = {
@@ -3309,12 +3324,16 @@ static const struct mv88e6xxx_ops mv88e6161_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6165_ops = {
@@ -3331,6 +3350,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops = { 
	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6171_ops = {
@@ -3346,12 +3366,16 @@ static const struct mv88e6xxx_ops mv88e6171_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6172_ops = {
@@ -3369,12 +3393,16 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6175_ops = {
@@ -3390,12 +3418,16 @@ static const struct mv88e6xxx_ops mv88e6175_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6176_ops = {
@@ -3413,12 +3445,16 @@ static const struct mv88e6xxx_ops mv88e6176_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6185_ops = {
@@ -3431,12 +3467,14 @@ static const struct mv88e6xxx_ops mv88e6185_ops = { 
	.port_set_speed = mv88e6185_port_set_speed,

	.port_set_frame_mode = mv88e6085_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,

	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6190_ops = {
@@ -3452,6 +3490,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_pause_config = mv88e6390_port_pause_config,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3459,6 +3498,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = { 
	.stats_get_stats = mv88e6390_stats_get_stats,

	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6390_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6190x_ops = {
@@ -3474,6 +3514,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_pause_config = mv88e6390_port_pause_config,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3481,6 +3522,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = { 
	.stats_get_stats = mv88e6390_stats_get_stats,

	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6390_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6191_ops = {
@@ -3496,6 +3538,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_pause_config = mv88e6390_port_pause_config,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3503,6 +3546,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = { 
	.stats_get_stats = mv88e6390_stats_get_stats,

	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6390_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6240_ops = {
@@ -3520,12 +3564,16 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6290_ops = {
@@ -3541,6 +3589,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_pause_config = mv88e6390_port_pause_config,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3548,6 +3597,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = { 
	.stats_get_stats = mv88e6390_stats_get_stats,

	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6390_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6320_ops = {
@@ -3564,12 +3614,16 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,

	.stats_get_strings = mv88e6320_stats_get_strings,

	.stats_get_stats = mv88e6320_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6321_ops = {
@@ -3586,6 +3640,9 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,

	.stats_get_strings = mv88e6320_stats_get_strings,
@@ -3607,12 +3664,16 @@ static const struct mv88e6xxx_ops mv88e6350_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6351_ops = {
@@ -3628,12 +3689,16 @@ static const struct mv88e6xxx_ops mv88e6351_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6352_ops = {
@@ -3651,12 +3716,16 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6097_port_pause_config,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_get_sset_count = mv88e6095_stats_get_sset_count,

	.stats_get_strings = mv88e6095_stats_get_strings,

	.stats_get_stats = mv88e6095_stats_get_stats,

	.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6095_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6390_ops = {
@@ -3672,6 +3741,9 @@ static const struct mv88e6xxx_ops mv88e6390_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6390_port_pause_config,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3679,6 +3751,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = { 
	.stats_get_stats = mv88e6390_stats_get_stats,

	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6390_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6390x_ops = {
@@ -3694,6 +3767,9 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_jumbo_config = mv88e6165_port_jumbo_config,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_config = mv88e6390_port_pause_config,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3701,6 +3777,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { 
	.stats_get_stats = mv88e6390_stats_get_stats,

	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6390_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,

};



static const struct mv88e6xxx_ops mv88e6391_ops = {
@@ -3716,6 +3793,7 @@ static const struct mv88e6xxx_ops mv88e6391_ops = { 
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,

	.port_set_ether_type = mv88e6351_port_set_ether_type,

	.port_pause_config = mv88e6390_port_pause_config,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3723,6 +3801,7 @@ static const struct mv88e6xxx_ops mv88e6391_ops = { 
	.stats_get_stats = mv88e6390_stats_get_stats,

	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,

	.g1_set_egress_port = mv88e6390_g1_set_egress_port,

	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,

};



static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,

drivers/net/dsa/mv88e6xxx/global1.c

+27 −0
Original line number Diff line number Diff line
@@ -102,6 +102,33 @@ int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 
					  port);

}



int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)

{

	int err;



	/* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */

	err = mv88e6390_g1_monitor_write(

		chip, GLOBAL_MONITOR_CONTROL_0180C280000000XLO, 0xff);

	if (err)

		return err;



	/* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */

	err = mv88e6390_g1_monitor_write(

		chip, GLOBAL_MONITOR_CONTROL_0180C280000000XHI, 0xff);

	if (err)

		return err;



	/* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */

	err = mv88e6390_g1_monitor_write(

		chip, GLOBAL_MONITOR_CONTROL_0180C280000002XLO, 0xff);

	if (err)

		return err;



	/* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */

	return mv88e6390_g1_monitor_write(

		chip, GLOBAL_MONITOR_CONTROL_0180C280000002XHI, 0xff);

}



/* Offset 0x1c: Global Control 2 */



int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)

drivers/net/dsa/mv88e6xxx/global1.h

+1 −0
Original line number Diff line number Diff line
@@ -29,5 +29,6 @@ int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port); 
int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);

int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);

int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);

int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);



#endif /* _MV88E6XXX_GLOBAL1_H */

drivers/net/dsa/mv88e6xxx/global2.c

+25 −18
Original line number Diff line number Diff line
@@ -38,6 +38,31 @@ static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 
	return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask);

}



/* Offset 0x02: Management Enable 2x */

/* Offset 0x03: Management Enable 0x */



int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)

{

	int err;



	/* Consider the frames with reserved multicast destination

	 * addresses matching 01:80:c2:00:00:2x as MGMT.

	 */

	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {

		err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);

		if (err)

			return err;

	}



	/* Consider the frames with reserved multicast destination

	 * addresses matching 01:80:c2:00:00:0x as MGMT.

	 */

	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X))

		return mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);



	return 0;

}



/* Offset 0x06: Device Mapping Table register */



static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
@@ -567,24 +592,6 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) 
	u16 reg;

	int err;



	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {

		/* Consider the frames with reserved multicast destination

		 * addresses matching 01:80:c2:00:00:2x as MGMT.

		 */

		err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);

		if (err)

			return err;

	}



	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {

		/* Consider the frames with reserved multicast destination

		 * addresses matching 01:80:c2:00:00:0x as MGMT.

		 */

		err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);

		if (err)

			return err;

	}



	/* Ignore removed tag data on doubly tagged packets, disable

	 * flow control messages, force flow control priority to the

	 * highest, and send all special multicast frames to the CPU

drivers/net/dsa/mv88e6xxx/global2.h

+6 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 
int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);

void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);

int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);



#else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
@@ -94,6 +95,11 @@ static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 
{

}



static inline int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)

{

	return -EOPNOTSUPP;

}



#endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */



#endif /* _MV88E6XXX_GLOBAL2_H */