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Commit ce7f2209 authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Use a different register to convey log info to GMU 



The GENERAL_6 scratch register is already used for some other
purpose. So, use GMU_PWR_COL_CP_MSG to convey the master log
base address and size to the GMU.

Change-Id: I9df720dffb594d745a8fb1506fc64000e2abe5d1
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent dc297960

drivers/gpu/msm/a6xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -957,6 +957,7 @@ 
#define A6XX_GMU_RPMH_CTRL			0x1F8E8

#define A6XX_GMU_RPMH_HYST_CTRL			0x1F8E9

#define A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE    0x1F8EC

#define A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG      0x1F900

#define A6XX_GMU_BOOT_KMD_LM_HANDSHAKE		0x1F9F0

#define A6XX_GMU_LLM_GLM_SLEEP_CTRL		0x1F957

#define A6XX_GMU_LLM_GLM_SLEEP_STATUS		0x1F958

drivers/gpu/msm/adreno_a6xx.c

+1 −1
Original line number Diff line number Diff line
@@ -2088,7 +2088,7 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device, 
			| (ADRENO_CHIPID_PATCH(adreno_dev->chipid) << 8);



	kgsl_gmu_regwrite(device, A6XX_GMU_HFI_SFR_ADDR, chipid);

	kgsl_gmu_regwrite(device, A6XX_GMU_GENERAL_6, gmu->gmu_log->gmuaddr);

	init_gmu_log_base(device);



	/* Configure power control and bring the GMU out of reset */

	a6xx_gmu_power_config(device);

drivers/gpu/msm/kgsl_gmu.c

+14 −2
Original line number Diff line number Diff line
@@ -71,10 +71,10 @@ struct gmu_iommu_context { 


#define DUMPMEM_SIZE SZ_16K



#define LOGMEM_SIZE SZ_4K



#define DUMMY_SIZE   SZ_4K



#define LOGMEM_SIZE  SZ_4K



/* Define target specific GMU VMA configurations */

static const struct gmu_vma vma = {

	/* Noncached user segment */
@@ -110,6 +110,18 @@ static unsigned long gmu_kmem_bitmap; 
static unsigned int num_uncached_entries;

static unsigned int num_cached_entries;



void init_gmu_log_base(struct kgsl_device *device)

{

	uint32_t gmu_log_info;

	struct gmu_device *gmu = &device->gmu;



	/* Log size is encoded in (number of 4K units - 1) */

	gmu_log_info = (gmu->gmu_log->gmuaddr & 0xFFFFF000) |

		((LOGMEM_SIZE/SZ_4K - 1) & 0xFF);

	kgsl_gmu_regwrite(device, A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,

			gmu_log_info);

}



static int _gmu_iommu_fault_handler(struct device *dev,

		unsigned long addr, int flags, const char *name)

{

drivers/gpu/msm/kgsl_gmu.h

+1 −0
Original line number Diff line number Diff line
@@ -267,4 +267,5 @@ int gmu_dcvs_set(struct gmu_device *gmu, unsigned int gpu_pwrlevel, 
		unsigned int bus_level);

int allocate_gmu_cached_fw(struct gmu_device *gmu);

bool is_cached_fw_size_valid(uint32_t size_in_bytes);

void init_gmu_log_base(struct kgsl_device *device);

#endif /* __KGSL_GMU_H */