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Commit ce137c04 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu:cg & pg shouldn't active on VF device 



CG & PG function changes engine clock/gating, which is
not appropriate for VF device, because one vf doesn't know
the whole picture of engine's overall workload.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cbabc8b3

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+9 −0
Original line number Diff line number Diff line
@@ -5841,6 +5841,9 @@ static int gfx_v8_0_set_powergating_state(void *handle, 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	bool enable = (state == AMD_PG_STATE_GATE) ? true : false;



	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->asic_type) {

	case CHIP_CARRIZO:

	case CHIP_STONEY:
@@ -5898,6 +5901,9 @@ static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int data;



	if (amdgpu_sriov_vf(adev))

		*flags = 0;



	/* AMD_CG_SUPPORT_GFX_MGCG */

	data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

	if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
@@ -6411,6 +6417,9 @@ static int gfx_v8_0_set_clockgating_state(void *handle, 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->asic_type) {

	case CHIP_FIJI:

	case CHIP_CARRIZO:

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+6 −0
Original line number Diff line number Diff line
@@ -1434,6 +1434,9 @@ static int gmc_v8_0_set_clockgating_state(void *handle, 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->asic_type) {

	case CHIP_FIJI:

		fiji_update_mc_medium_grain_clock_gating(adev,
@@ -1458,6 +1461,9 @@ static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int data;



	if (amdgpu_sriov_vf(adev))

		*flags = 0;



	/* AMD_CG_SUPPORT_MC_MGCG */

	data = RREG32(mmMC_HUB_MISC_HUB_CG);

	if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+6 −0
Original line number Diff line number Diff line
@@ -1512,6 +1512,9 @@ static int sdma_v3_0_set_clockgating_state(void *handle, 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->asic_type) {

	case CHIP_FIJI:

	case CHIP_CARRIZO:
@@ -1538,6 +1541,9 @@ static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int data;



	if (amdgpu_sriov_vf(adev))

		*flags = 0;



	/* AMD_CG_SUPPORT_SDMA_MGCG */

	data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);

	if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))

drivers/gpu/drm/amd/amdgpu/vi.c

+6 −0
Original line number Diff line number Diff line
@@ -1391,6 +1391,9 @@ static int vi_common_set_clockgating_state(void *handle, 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->asic_type) {

	case CHIP_FIJI:

		vi_update_bif_medium_grain_light_sleep(adev,
@@ -1435,6 +1438,9 @@ static void vi_common_get_clockgating_state(void *handle, u32 *flags) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int data;



	if (amdgpu_sriov_vf(adev))

		*flags = 0;



	/* AMD_CG_SUPPORT_BIF_LS */

	data = RREG32_PCIE(ixPCIE_CNTL2);

	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)