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Commit cdae1730 authored by Mike Turquette's avatar Mike Turquette
Browse files

Merge branch 'clk-fixes' into clk-next

parents fb2b3c9f c556bcdd

drivers/clk/clk-s2mps11.c

+2 −5
Original line number Diff line number Diff line
@@ -219,16 +219,13 @@ static int s2mps11_clk_probe(struct platform_device *pdev) 
			goto err_reg;

		}



		s2mps11_clk->lookup = devm_kzalloc(&pdev->dev,

					sizeof(struct clk_lookup), GFP_KERNEL);

		s2mps11_clk->lookup = clkdev_alloc(s2mps11_clk->clk,

					s2mps11_name(s2mps11_clk), NULL);

		if (!s2mps11_clk->lookup) {

			ret = -ENOMEM;

			goto err_lup;

		}



		s2mps11_clk->lookup->con_id = s2mps11_name(s2mps11_clk);

		s2mps11_clk->lookup->clk = s2mps11_clk->clk;



		clkdev_add(s2mps11_clk->lookup);

	}

drivers/clk/qcom/mmcc-msm8960.c

+1 −1
Original line number Diff line number Diff line
@@ -1209,7 +1209,7 @@ static struct clk_branch rot_clk = { 


static u8 mmcc_pxo_hdmi_map[] = {

	[P_PXO]		= 0,

	[P_HDMI_PLL]	= 2,

	[P_HDMI_PLL]	= 3,

};



static const char *mmcc_pxo_hdmi[] = {

drivers/clk/samsung/clk-exynos4.c

+4 −12
Original line number Diff line number Diff line
@@ -925,21 +925,13 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 
	GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,

			0, 0),

	GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),

	GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp",

			E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre",

			E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre",

			E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",

			E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp",

	GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",

			E4X12_GATE_IP_ISP, 0, 0, 0),

	GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp",

	GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",

			E4X12_GATE_IP_ISP, 1, 0, 0),

	GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp",

	GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",

			E4X12_GATE_IP_ISP, 2, 0, 0),

	GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp",

	GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",

			E4X12_GATE_IP_ISP, 3, 0, 0),

	GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),

	GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,

drivers/clk/samsung/clk-exynos5250.c

+1 −1
Original line number Diff line number Diff line
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 
	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),

	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),

	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",

			GATE_IP_DISP1, 2, 0, 0),

			GATE_IP_DISP1, 9, 0, 0),

	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",

			GATE_IP_DISP1, 8, 0, 0),

	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),

drivers/clk/samsung/clk-exynos5420.c

+55 −30
Original line number Diff line number Diff line
@@ -890,8 +890,6 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { 
			GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),

	GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",

			GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",

			GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),

	GATE(0, "aclk266_isp", "mout_user_aclk266_isp",

			GATE_BUS_TOP, 13, 0, 0),

	GATE(0, "aclk166", "mout_user_aclk166",
@@ -994,34 +992,61 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { 
			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),



	/* PERIC Block */

	GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),

	GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_IP_PERIC, 1, 0, 0),

	GATE(CLK_UART2, "uart2", "aclk66_peric", GATE_IP_PERIC, 2, 0, 0),

	GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_IP_PERIC, 3, 0, 0),

	GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_IP_PERIC, 6, 0, 0),

	GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_IP_PERIC, 7, 0, 0),

	GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_IP_PERIC, 8, 0, 0),

	GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_IP_PERIC, 9, 0, 0),

	GATE(CLK_USI0, "usi0", "aclk66_peric", GATE_IP_PERIC, 10, 0, 0),

	GATE(CLK_USI1, "usi1", "aclk66_peric", GATE_IP_PERIC, 11, 0, 0),

	GATE(CLK_USI2, "usi2", "aclk66_peric", GATE_IP_PERIC, 12, 0, 0),

	GATE(CLK_USI3, "usi3", "aclk66_peric", GATE_IP_PERIC, 13, 0, 0),

	GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_IP_PERIC, 14, 0, 0),

	GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_IP_PERIC, 15, 0, 0),

	GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_IP_PERIC, 16, 0, 0),

	GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_IP_PERIC, 17, 0, 0),

	GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_IP_PERIC, 18, 0, 0),

	GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_IP_PERIC, 20, 0, 0),

	GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_IP_PERIC, 21, 0, 0),

	GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_IP_PERIC, 22, 0, 0),

	GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_IP_PERIC, 23, 0, 0),

	GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_IP_PERIC, 24, 0, 0),

	GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_IP_PERIC, 26, 0, 0),

	GATE(CLK_USI4, "usi4", "aclk66_peric", GATE_IP_PERIC, 28, 0, 0),

	GATE(CLK_USI5, "usi5", "aclk66_peric", GATE_IP_PERIC, 30, 0, 0),

	GATE(CLK_USI6, "usi6", "aclk66_peric", GATE_IP_PERIC, 31, 0, 0),



	GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),

	GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 0, 0, 0),

	GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 1, 0, 0),

	GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 2, 0, 0),

	GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 3, 0, 0),

	GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 6, 0, 0),

	GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 7, 0, 0),

	GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 8, 0, 0),

	GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 9, 0, 0),

	GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 10, 0, 0),

	GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 11, 0, 0),

	GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 12, 0, 0),

	GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 13, 0, 0),

	GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 14, 0, 0),

	GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 15, 0, 0),

	GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 16, 0, 0),

	GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 17, 0, 0),

	GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 18, 0, 0),

	GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 20, 0, 0),

	GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 21, 0, 0),

	GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 22, 0, 0),

	GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 23, 0, 0),

	GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 24, 0, 0),

	GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 26, 0, 0),

	GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 28, 0, 0),

	GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 30, 0, 0),

	GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",

			GATE_IP_PERIC, 31, 0, 0),



	GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",

			GATE_BUS_PERIC, 22, 0, 0),



	/* PERIS Block */

	GATE(CLK_CHIPID, "chipid", "aclk66_psgen",