Commit ccaf725a authored Apr 18, 2017 by Benjamin Herrenschmidt Committed by David S. Miller Apr 18, 2017

ftgmac100: Fix potential ordering issue in NAPI poll



We need to ensure the loads from the descriptor are done after the
MMIO store clearing the interrupts has completed, otherwise we
might still miss work.

A read back from the MMIO register will "push" the posted store and
ioread32 has a barrier on weakly aordered architectures that will
order subsequent accesses.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 33de6932

drivers/net/ethernet/faraday/ftgmac100.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -1349,6 +1349,13 @@ static int ftgmac100_poll(struct napi_struct *napi, int budget)
		*/
		iowrite32(FTGMAC100_INT_RXTX,
		priv->base + FTGMAC100_OFFSET_ISR);

		/* Push the above (and provides a barrier vs. subsequent
		* reads of the descriptor).
		*/
		ioread32(priv->base + FTGMAC100_OFFSET_ISR);

		/* Check RX and TX descriptors for more work to do */
		if (ftgmac100_check_rx(priv) \|\|
		ftgmac100_tx_buf_cleanable(priv))
		return budget;