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Commit cc769b62 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
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drm/i915: don't recheck for invalid pipe bpp



As noticed by Daniel Vetter, intel_pipe_choose_bpp_dither should
already check for invalid bpp values and set a valid value, so remove
the recheck inside ironlake_crtc_mode_set and also replace a "default"
switch case inside ironlake_set_pipeconf with a BUG().

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 398b7a1b
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+3 −12
Original line number Diff line number Diff line
@@ -4626,8 +4626,8 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
		val |= PIPE_12BPC;
		break;
	default:
		val |= PIPE_8BPC;
		break;
		/* Case prevented by intel_choose_pipe_bpp_dither. */
		BUG();
	}

	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
@@ -4728,7 +4728,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
	struct fdi_m_n m_n = {0};
	u32 temp;
	int target_clock, pixel_multiplier, lane, link_bw, factor;
	unsigned int pipe_bpp;
	bool dither;
	bool is_cpu_edp = false, is_pch_edp = false;

@@ -4802,18 +4801,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
		target_clock = adjusted_mode->clock;

	/* determine panel color depth */
	dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
	dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
	if (is_lvds && dev_priv->lvds_dither)
		dither = true;

	if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
	    pipe_bpp != 36) {
		WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
		     pipe_bpp);
		pipe_bpp = 24;
	}
	intel_crtc->bpp = pipe_bpp;

	if (!lane) {
		/*
		 * Account for spread spectrum to avoid