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Commit cc01e8fa authored by Kyle Piefer's avatar Kyle Piefer Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Bypass GMU caches at boot 



Prior to firmware execution, the GMU icache and dcache
could contain stale information. To prevent instability,
bypass them at boot and enable them in the firmware.

Change-Id: Idff4fb92293533e6b6ed397e58dd1b410bec5496
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent e6cca5ba

drivers/gpu/msm/a6xx_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -926,6 +926,8 @@ 
#define A6XX_GMU_DCVS_PERF_SETTING		0x1CBFD

#define A6XX_GMU_DCVS_BW_SETTING		0x1CBFE

#define A6XX_GMU_DCVS_RETURN			0x1CBFF

#define A6XX_GMU_ICACHE_CONFIG			0x1F400

#define A6XX_GMU_DCACHE_CONFIG			0x1F401

#define A6XX_GMU_SYS_BUS_CONFIG			0x1F40F

#define A6XX_GMU_CM3_SYSRESET			0x1F800

#define A6XX_GMU_CM3_BOOT_CONFIG		0x1F801

drivers/gpu/msm/adreno_a6xx.c

+3 −1
Original line number Diff line number Diff line
@@ -1466,8 +1466,10 @@ static void a6xx_gmu_power_config(struct kgsl_device *device) 


	/* Configure registers for idle setting. The setting is cumulative */



	/* Disable GMU WB/RB buffer */

	/* Disable GMU WB/RB buffer and caches at boot */

	kgsl_gmu_regwrite(device, A6XX_GMU_SYS_BUS_CONFIG, 0x1);

	kgsl_gmu_regwrite(device, A6XX_GMU_ICACHE_CONFIG, 0x1);

	kgsl_gmu_regwrite(device, A6XX_GMU_DCACHE_CONFIG, 0x1);



	kgsl_gmu_regwrite(device,

		A6XX_GMU_PWR_COL_INTER_FRAME_CTRL,  0x9C40400);