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Commit cac3576b authored by Krishna Manikandan's avatar Krishna Manikandan Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add display dt node for atoll target 



Add all display related dt nodes for atoll target.

Change-Id: I47e61a7758d4cdda7520d72d9bc42381f06f05c9
Signed-off-by: default avatarKrishna Manikandan <mkrishn@codeaurora.org>
parent 29444f60

arch/arm64/boot/dts/qcom/atoll-sde.dtsi

0 → 100644
+402 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/clock/mdss-7nm-pll-clk.h>



&soc {

	mdss_mdp: qcom,mdss_mdp@ae00000 {

		compatible = "qcom,sde-kms";

		reg = <0xae00000 0x84208>,

		      <0xaeb0000 0x2008>,

		      <0xaeac000 0x214>,

		      <0xae8f000 0x02c>;

		reg-names = "mdp_phys",

			"vbif_phys",

			"regdma_phys",

			"sid_phys";



		clocks =

			<&clock_gcc GCC_DISP_AHB_CLK>,

			<&clock_gcc GCC_DISP_HF_AXI_CLK>,

			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,

			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,

			<&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

			<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;

		clock-names = "gcc_iface", "gcc_bus", "iface_clk",

				"core_clk", "vsync_clk",

				"lut_clk", "rot_clk";

		clock-rate = <0 0 0 300000000 19200000 200000000

						200000000>;

		clock-max-rate = <0 0 0 460000000 19200000 460000000

						460000000>;



		sde-vdd-supply = <&mdss_core_gdsc>;



		/* interrupt config */

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <1>;

		iommus = <&apps_smmu 0x800 0x2>;



		#address-cells = <1>;

		#size-cells = <0>;



		#power-domain-cells = <0>;



		/* hw blocks */

		qcom,sde-off = <0x1000>;

		qcom,sde-len = <0x494>;



		qcom,sde-ctl-off = <0x2000 0x2200 0x2400>;

		qcom,sde-ctl-size = <0x1dc>;

		qcom,sde-ctl-display-pref = "primary", "none", "none";



		qcom,sde-mixer-off = <0x45000 0x46000>;

		qcom,sde-mixer-size = <0x320>;

		qcom,sde-mixer-display-pref = "primary", "none";



		qcom,sde-mixer-cwb-pref = "none", "cwb";



		qcom,sde-dspp-top-off = <0x1300>;

		qcom,sde-dspp-top-size = <0x80>;

		qcom,sde-dspp-off = <0x55000>;

		qcom,sde-dspp-size = <0x1800>;



		qcom,sde-wb-off = <0x66000>;

		qcom,sde-wb-size = <0x2c8>;

		qcom,sde-wb-xin-id = <6>;

		qcom,sde-wb-id = <2>;

		qcom,sde-wb-clk-ctrl = <0x3b8 24>;



		qcom,sde-intf-off = <0x6b000 0x6b800>;

		qcom,sde-intf-size = <0x2b8>;

		qcom,sde-intf-type = "dp", "dsi";



		qcom,sde-pp-off = <0x71000 0x71800>;

		qcom,sde-pp-slave = <0x0 0x0>;

		qcom,sde-pp-size = <0xd4>;

		qcom,sde-pp-merge-3d-id = <0x0 0x0>;



		qcom,sde-merge-3d-off = <0x84000>;

		qcom,sde-merge-3d-size = <0x100>;



		qcom,sde-te2-off = <0x2000 0x2000>;



		qcom,sde-cdm-off = <0x7a200>;

		qcom,sde-cdm-size = <0x224>;



		qcom,sde-dither-off = <0x30e0 0x30e0>;

		qcom,sde-dither-version = <0x00010000>;

		qcom,sde-dither-size = <0x20>;



		qcom,sde-sspp-type = "vig", "dma", "dma", "dma";



		qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000>;

		qcom,sde-sspp-src-size = <0x1f8>;



		qcom,sde-sspp-xin-id = <0 1 5 9 >;

		qcom,sde-sspp-excl-rect = <1 1 1 1>;

		qcom,sde-sspp-smart-dma-priority = <4 1 2 3>;

		qcom,sde-smart-dma-rev = "smart_dma_v2p5";



		qcom,sde-mixer-pair-mask = <2 1>;



		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98

						0xb0 0xc8 0xe0 0xf8 0x110>;



		qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000

						 2600000 2600000>;



		qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000

						 2600000 2600000>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */

		qcom,sde-sspp-clk-ctrl =

				<0x2ac 0>, <0x2b4 8>,

				 <0x2ac 8>, <0x2c4 8>;

		qcom,sde-sspp-csc-off = <0x1a00>;

		qcom,sde-csc-type = "csc-10bit";

		qcom,sde-qseed-type = "qseedv3lite";

		qcom,sde-sspp-qseed-off = <0xa00>;

		qcom,sde-mixer-linewidth = <2560>;

		qcom,sde-sspp-linewidth = <2160>;

		qcom,sde-vig-sspp-linewidth = <4096>;

		qcom,sde-wb-linewidth = <1080>;

		qcom,sde-mixer-blendstages = <0x7>;

		qcom,sde-highest-bank-bit = <0x1>;

		qcom,sde-ubwc-version = <0x200>;

		qcom,sde-ubwc-bw-calc-version = <0x1>;

		qcom,sde-ubwc-static = <0x18>;

		qcom,sde-panic-per-pipe;

		qcom,sde-smart-panel-align-mode = <0xc>;

		qcom,sde-has-cdp;

		qcom,sde-has-src-split;

		qcom,sde-pipe-order-version = <0x1>;

		qcom,sde-has-dim-layer;

		qcom,sde-has-idle-pc;



		qcom,sde-max-bw-low-kbps = <3900000>;

		qcom,sde-max-bw-high-kbps = <5500000>;

		qcom,sde-min-core-ib-kbps = <2400000>;

		qcom,sde-min-llcc-ib-kbps = <800000>;

		qcom,sde-min-dram-ib-kbps = <800000>;

		qcom,sde-dram-channels = <2>;

		qcom,sde-num-nrt-paths = <0>;



		qcom,sde-vbif-off = <0>;

		qcom,sde-vbif-size = <0x1040>;

		qcom,sde-vbif-id = <0>;

		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;

		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;



		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;

		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

		qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;

		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;



		/* macrotile & macrotile-qseed has the same configs */

		qcom,sde-danger-lut = <0x000000ff 0x0000ffff

			0x00000000 0x00000000 0x0000ffff>;



		qcom,sde-safe-lut-linear = <0 0xfff0>;

		qcom,sde-safe-lut-macrotile = <0 0xff00>;

		/* same as safe-lut-macrotile */

		qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;

		qcom,sde-safe-lut-nrt = <0 0xffff>;

		qcom,sde-safe-lut-cwb = <0 0x3ff>;



		qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;

		qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;

		qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;

		qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;

		qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;



		qcom,sde-cdp-setting = <1 1>, <1 0>;



		qcom,sde-qos-cpu-mask = <0x3>;

		qcom,sde-qos-cpu-dma-latency = <300>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */



		qcom,sde-reg-dma-off = <0>;

		qcom,sde-reg-dma-version = <0x00010002>;

		qcom,sde-reg-dma-trigger-off = <0x119c>;

		qcom,sde-reg-dma-xin-id = <7>;

		qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;



		qcom,sde-secure-sid-mask = <0x801>;



		qcom,sde-sspp-vig-blocks {

			qcom,sde-vig-csc-off = <0x1a00>;

			qcom,sde-vig-qseed-off = <0xa00>;

			qcom,sde-vig-qseed-size = <0xa0>;

			qcom,sde-vig-gamut = <0x1d00 0x00060000>;

			qcom,sde-vig-igc = <0x1d00 0x00060000>;

			qcom,sde-vig-inverse-pma;

		};



		qcom,sde-sspp-dma-blocks {

			dgm@0 {

				qcom,sde-dma-igc = <0x400 0x00050000>;

				qcom,sde-dma-gc = <0x600 0x00050000>;

				qcom,sde-dma-inverse-pma;

				qcom,sde-dma-csc-off = <0x200>;

			};



			dgm@1 {

				qcom,sde-dma-igc = <0x1400 0x00050000>;

				qcom,sde-dma-gc = <0x600 0x00050000>;

				qcom,sde-dma-inverse-pma;

				qcom,sde-dma-csc-off = <0x1200>;

			};

		};



		qcom,sde-dspp-blocks {

			qcom,sde-dspp-igc = <0x0 0x00030001>;

			qcom,sde-dspp-hsic = <0x800 0x00010007>;

			qcom,sde-dspp-memcolor = <0x880 0x00010007>;

			qcom,sde-dspp-hist = <0x800 0x00010007>;

			qcom,sde-dspp-sixzone= <0x900 0x00010007>;

			qcom,sde-dspp-vlut = <0xa00 0x00010008>;

			qcom,sde-dspp-gamut = <0x1000 0x00040002>;

			qcom,sde-dspp-pcc = <0x1700 0x00040000>;

			qcom,sde-dspp-gc = <0x17c0 0x00010008>;

			qcom,sde-dspp-dither = <0x82c 0x00010007>;

		};



		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



		qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "sde-vdd";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};



		smmu_sde_sec: qcom,smmu_sde_sec_cb {

			compatible = "qcom,smmu_sde_sec";

			iommus = <&apps_smmu 0x801 0x0>;

		};



		/* data and reg bus scale settings */

		qcom,sde-data-bus {

			qcom,msm-bus,name = "mdss_sde";

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<22 512 0 0>,

				<22 512 0 6400000>,

				<22 512 0 6400000>;

		};



		qcom,sde-reg-bus {

			qcom,msm-bus,name = "mdss_reg";

			qcom,msm-bus,num-cases = <4>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<1 590 0 0>,

				<1 590 0 76800>,

				<1 590 0 150000>,

				<1 590 0 300000>;

		};

	};



	sde_rscc: qcom,sde_rscc@af20000 {

		cell-index = <0>;

		compatible = "qcom,sde-rsc";

		reg = <0xaf20000 0x3c50>,

			<0xaf30000 0x3fd4>;

		reg-names = "drv", "wrapper";

		qcom,sde-rsc-version = <3>;

		status = "disabled";



		qcom,sde-dram-channels = <2>;



		mboxes = <&disp_rsc 0>;

		mbox-names = "disp_rsc";



		vdd-supply = <&mdss_core_gdsc>;

		clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,

			<&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,

			<&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;

		clock-names = "vsync_clk", "gdsc_clk", "iface_clk";



		/* data and reg bus scale settings */

		qcom,sde-data-bus {

			qcom,msm-bus,name = "disp_rsc_mnoc";

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

			    <20003 20515 0 0>,

			    <20003 20515 0 6400000>,

			    <20003 20515 0 6400000>;

		};



		qcom,sde-llcc-bus {

			qcom,msm-bus,name = "disp_rsc_llcc";

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

			    <20001 20513 0 0>,

			    <20001 20513 0 6400000>,

			    <20001 20513 0 6400000>;

		};



		qcom,sde-ebi-bus {

			qcom,msm-bus,name = "disp_rsc_ebi";

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

			    <20000 20512 0 0>,

			    <20000 20512 0 6400000>,

			    <20000 20512 0 6400000>;

		};

	};



	mdss_rotator: qcom,mdss_rotator@aea8800 {

		compatible = "qcom,sde_rotator";

		reg = <0xae00000 0xac000>,

		      <0xaeb8000 0x3000>;

		reg-names = "mdp_phys",

			"rot_vbif_phys";



		#list-cells = <1>;



		qcom,mdss-rot-mode = <1>;

		qcom,mdss-highest-bank-bit = <0x1>;



		/* Bus Scale Settings */

		qcom,msm-bus,name = "mdss_rotator";

		qcom,msm-bus,num-cases = <3>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<25 512 0 0>,

			<25 512 0 6400000>,

			<25 512 0 6400000>;



		rot-vdd-supply = <&mdss_core_gdsc>;

		qcom,supply-names = "rot-vdd";



		clocks =

			<&clock_gcc GCC_DISP_AHB_CLK>,

			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;

		clock-names = "gcc_iface", "iface_clk", "rot_clk";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <2 0>;



		power-domains = <&mdss_mdp>;



		/* Offline rotator QoS setting */

		qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;

		qcom,mdss-rot-vbif-memtype = <3 3>;

		qcom,mdss-rot-cdp-setting = <1 1>;

		qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;

		qcom,mdss-rot-danger-lut = <0x0 0x0>;

		qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;



		qcom,mdss-default-ot-rd-limit = <32>;

		qcom,mdss-default-ot-wr-limit = <32>;



		qcom,mdss-sbuf-headroom = <20>;



		/* reg bus scale settings */

		rot_reg: qcom,rot-reg-bus {

			qcom,msm-bus,name = "mdss_rot_reg";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<1 590 0 0>,

				<1 590 0 76800>;

		};



		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {

			compatible = "qcom,smmu_sde_rot_unsec";

			iommus = <&apps_smmu 0xC1C 0x0>;

		};



		smmu_rot_sec: qcom,smmu_rot_sec_cb {

			compatible = "qcom,smmu_sde_rot_sec";

			iommus = <&apps_smmu 0xC1D 0x0>;

		};

	};

};