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Commit c972bc72 authored Nov 05, 2018 by Jilai Wang Committed by Ashwini Muduganti Nov 12, 2018

ARM: dts: msm: Add vreg property in npu power level nodes



Add vreg property in npu power level nodes to indicate the
actual power level for each set of clock frequency settings.

Change-Id: I07ba2893c09ef97d4b5d280350fdbec1428e9ead
Signed-off-by: Jilai Wang <jilaiw@codeaurora.org>

parent 660a68f2

arch/arm64/boot/dts/qcom/sdmmagpie-npu.dtsi

+5 −0

Original line number	Diff line number	Diff line
		@@ -75,6 +75,7 @@
		initial-pwrlevel = <4>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <300000000
		19200000
		100000000
		@@ -96,6 +97,7 @@
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <400000000
		19200000
		150000000
		@@ -117,6 +119,7 @@
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <466500000
		19200000
		200000000
		@@ -138,6 +141,7 @@
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <600000000
		19200000
		300000000
		@@ -159,6 +163,7 @@
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <700000000
		19200000
		400000000

arch/arm64/boot/dts/qcom/sm8150-npu.dtsi

+5 −0

Original line number	Diff line number	Diff line
		@@ -78,6 +78,7 @@
		initial-pwrlevel = <4>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <300000000
		19200000
		100000000
		@@ -101,6 +102,7 @@
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <350000000
		19200000
		150000000
		@@ -124,6 +126,7 @@
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <400000000
		19200000
		200000000
		@@ -147,6 +150,7 @@
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <600000000
		19200000
		300000000
		@@ -170,6 +174,7 @@
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <715000000
		19200000
		350000000

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -697,6 +697,7 @@
		initial-pwrlevel = <5>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <300000000
		19200000
		100000000
		@@ -720,6 +721,7 @@
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <400000000
		19200000
		150000000
		@@ -743,6 +745,7 @@
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <487000000
		19200000
		200000000
		@@ -766,6 +769,7 @@
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <652000000
		19200000
		300000000
		@@ -789,6 +793,7 @@
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <811000000
		19200000
		400000000
		@@ -812,6 +817,7 @@
		};
		qcom,npu-pwrlevel@5 {
		reg = <5>;
		vreg = <7>;
		clk-freq = <908000000
		19200000
		400000000