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Commit c94c824e authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: do not disable gpu_cx_gdsc for SM8150"

parents d56101b7 33ac7ac9

Documentation/devicetree/bindings/regulator/gdsc-regulator.txt

+6 −0
Original line number Diff line number Diff line
@@ -43,6 +43,12 @@ Optional properties: 
			Ex. "base", "domain-addr", "sw-reset", "hw-ctrl-addr".

 - qcom,no-status-check-on-disable: Do not poll the status bit when GDSC

			is disabled.

 - qcom,skip-disable:	Boolean flag indicating that the GDSC must not be

			physically disabled upon a software disable request.

			Instead, the GDSC will be disabled by the always-on

			processor (AOP) upon entering system sleep.  The AOP

			will also perform a special reset sequence for the GDSC

			upon resuming from system sleep.

 - qcom,disallow-clear: Presence denotes the periph & core memory will not be

			cleared, unless the required subsystem does not invoke

			the api which will allow clearing the bits.

arch/arm64/boot/dts/qcom/sm8150-gdsc.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ 
		regulator-name = "gpu_cx_gdsc";

		reg = <0x2c9106c 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,skip-disable;

		qcom,gds-timeout = <500>;

		qcom,clk-dis-wait-val = <8>;

		status = "disabled";

drivers/clk/qcom/gdsc-regulator.c

+16 −1
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ struct gdsc { 
	bool			root_en;

	bool			force_root_en;

	bool			no_status_check_on_disable;

	bool			skip_disable;

	bool			is_gdsc_enabled;

	bool			allow_clear;

	bool			reset_aon;
@@ -150,6 +151,13 @@ static int gdsc_is_enabled(struct regulator_dev *rdev) 
	int ret;

	bool is_enabled = false;



	/*

	 * Return the logical GDSC enable state given that it will only be

	 * physically disabled by AOP during system sleep.

	 */

	if (sc->skip_disable)

		return sc->is_gdsc_enabled;



	if (!sc->toggle_logic)

		return !sc->resets_asserted;
@@ -418,7 +426,12 @@ static int gdsc_disable(struct regulator_dev *rdev) 
	/* Delay to account for staggered memory powerdown. */

	udelay(1);



	if (sc->toggle_logic) {

	if (sc->skip_disable) {

		/*

		 * Don't change the GDSCR register state on disable.  AOP will

		 * handle this during system sleep.

		 */

	} else if (sc->toggle_logic) {

		regmap_read(sc->regmap, REG_OFFSET, &regval);

		regval |= SW_COLLAPSE_MASK;

		regmap_write(sc->regmap, REG_OFFSET, regval);
@@ -831,6 +844,8 @@ static int gdsc_probe(struct platform_device *pdev) 
	sc->no_status_check_on_disable =

			of_property_read_bool(pdev->dev.of_node,

					"qcom,no-status-check-on-disable");

	sc->skip_disable = of_property_read_bool(pdev->dev.of_node,

					"qcom,skip-disable");

	retain_mem = of_property_read_bool(pdev->dev.of_node,

					    "qcom,retain-mem");

	sc->toggle_mem = !retain_mem;