Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c861519f authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: Fix delay loops which may be removed by GCC. 



GCC 4.1 and newer remove empty loops.  This becomes a problem when delay
loops get removed.  Fixed by rewriting to user the proper Linux interface
for such delays.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Reported-by: default avatarRasmus Villemoes <linux@rasmusvillemoes.dk>
Acked-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 1ec21837

arch/mips/pci/pci-rt2880.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -11,6 +11,7 @@ 
 *  by the Free Software Foundation.

 *  by the Free Software Foundation.

 */

 */





#include <linux/delay.h>

#include <linux/types.h>

#include <linux/types.h>

#include <linux/pci.h>

#include <linux/pci.h>

#include <linux/io.h>

#include <linux/io.h>
@@ -232,8 +233,7 @@ static int rt288x_pci_probe(struct platform_device *pdev) 
	ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;

	ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;





	rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);

	rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);

	for (i = 0; i < 0xfffff; i++)

	udelay(1);

		;





	rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);

	rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);

	rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);

	rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);

arch/mips/pmcs-msp71xx/msp_setup.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -10,6 +10,8 @@ 
 * option) any later version.

 * option) any later version.

 */

 */





#include <linux/delay.h>



#include <asm/bootinfo.h>

#include <asm/bootinfo.h>

#include <asm/cacheflush.h>

#include <asm/cacheflush.h>

#include <asm/idle.h>

#include <asm/idle.h>
@@ -77,7 +79,7 @@ void msp7120_reset(void) 
	 */

	 */





	/* Wait a bit for the DDRC to settle */

	/* Wait a bit for the DDRC to settle */

	for (i = 0; i < 100000000; i++);

	mdelay(125);





#if defined(CONFIG_PMC_MSP7120_GW)

#if defined(CONFIG_PMC_MSP7120_GW)

	/*

	/*

arch/mips/sni/reset.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -3,6 +3,8 @@ 
 *

 *

 *  Reset a SNI machine.

 *  Reset a SNI machine.

 */

 */

#include <linux/delay.h>



#include <asm/io.h>

#include <asm/io.h>

#include <asm/reboot.h>

#include <asm/reboot.h>

#include <asm/sni.h>

#include <asm/sni.h>
@@ -32,9 +34,9 @@ void sni_machine_restart(char *command) 
	for (;;) {

	for (;;) {

		for (i = 0; i < 100; i++) {

		for (i = 0; i < 100; i++) {

			kb_wait();

			kb_wait();

			for (j = 0; j < 100000 ; j++)

			udelay(50);

				/* nothing */;

			outb_p(0xfe, 0x64);	 /* pulse reset low */

			outb_p(0xfe, 0x64);	 /* pulse reset low */

			udelay(50);

		}

		}

	}

	}

}

}