ARM: dts: msm: Add GPU properties for QCS405

/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

&soc {

	msm_bus: qcom,kgsl-busmon {

		label = "kgsl-busmon";

		compatible = "qcom,kgsl-busmon";

	};

	gpu_bw_tbl: gpu-bw-tbl {

		compatible = "operating-points-v2";

		opp-0   { opp-hz = /bits/ 64 < 0 >;    }; /* OFF */

		opp-100 { opp-hz = /bits/ 64 < 769 >;  }; /* 1. DDR:100.80MHz */

		opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. DDR:211.20MHz */

		opp-297 { opp-hz = /bits/ 64 < 2270 >; }; /* 3. DDR:297.60MHz */

		opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. DDR:384.00MHz */

		opp-556 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. DDR:556.80MHz */

		opp-595 { opp-hz = /bits/ 64 < 4541 >; }; /* 6. DDR:595.20MHz */

		opp-672 { opp-hz = /bits/ 64 < 5126 >; }; /* 7. DDR:672.00MHz */

		opp-740 { opp-hz = /bits/ 64 < 5639 >; }; /* 8. DDR:739.20MHz */

	};

	/* Bus governor */

	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		operating-points-v2 = <&gpu_bw_tbl>;

	};

	msm_gpu: qcom,kgsl-3d0@1c00000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		reg = <0x1c00000 0x10000

		       0x1c10000 0x10000>;

		reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";

		interrupts = <0 33 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;

		qcom,chipid = <0x03000620>;

		qcom,initial-pwrlevel = <3>;

		qcom,idle-timeout = <80>; //msecs

		qcom,strtstp-sleepwake;

		qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz

		clocks = <&clock_gcc GCC_OXILI_GFX3D_CLK>,

			<&clock_gcc GCC_OXILI_AHB_CLK>,

			<&clock_gcc GCC_BIMC_GFX_CLK>,

			<&clock_gcc GCC_BIMC_GPU_CLK>,

			<&clock_gcc GCC_GTCU_AHB_CLK>,

			<&clock_gcc GCC_GFX_TCU_CLK>,

			<&clock_gcc GCC_GFX_TBU_CLK>,

			<&clock_rpmcc RPM_SMD_BIMC_GPU_CLK>;

		clock-names = "core_clk", "iface_clk", "mem_iface_clk",

				"alt_mem_iface_clk", "gtcu_iface_clk",

				"gtcu_clk", "gtbu_clk", "bimc_gpu_clk";

		/* Bus Scale Settings */

		qcom,gpubw-dev = <&gpubw>;

		qcom,bus-control;

		qcom,bus-width = <16>;

		qcom,msm-bus,name = "grp3d";

		qcom,msm-bus,num-cases = <9>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<26 512 0 0>,       /*    off        */

				<26 512 0 806400>,  /* 1. 100.80 MHz */

				<26 512 0 1689600>, /* 2. 211.20 MHz */

				<26 512 0 2380800>, /* 3. 297.60 MHz */

				<26 512 0 3072000>, /* 4. 384.00 MHz */

				<26 512 0 4454400>, /* 5. 556.80 MHz */

				<26 512 0 4761600>, /* 6. 595.20 MHz */

				<26 512 0 5376000>, /* 7. 672.00 MHz */

				<26 512 0 5913600>; /* 8. 739.20 MHz */

		/* GDSC regulator names */

		regulator-names = "vdd";

		/* GDSC oxili regulators */

		vdd-supply = <&gdsc_oxili_gx>;

		/* CPU latency parameter */

		qcom,pm-qos-active-latency = <651>;

		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <598000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <7>;

				qcom,bus-max = <7>;

			};

			/* NOM+ */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <523200000>;

				qcom,bus-freq = <6>;

				qcom,bus-min = <5>;

				qcom,bus-max = <7>;

			};

			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <484800000>;

				qcom,bus-freq = <5>;

				qcom,bus-min = <4>;

				qcom,bus-max = <6>;

			};

			/* SVS+ */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

			};

			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <270000000>;

				qcom,bus-freq = <3>;

				qcom,bus-min = <1>;

				qcom,bus-max = <3>;

			};

			/* XO */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

		};

	};

};

	kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x1f00000 0x10000>;

		/*

		 * The gpu can only program a single context bank

		 * at this fixed offset.

		 */

		qcom,protect = <0xa000 0x1000>;

		clocks = <&clock_gcc GCC_SMMU_CFG_CLK>,

			<&clock_gcc GCC_GFX_TCU_CLK>,

			<&clock_gcc GCC_GTCU_AHB_CLK>,

			<&clock_gcc GCC_GFX_TBU_CLK>;

		clock-names = "scfg_clk", "gtcu_clk", "gtcu_iface_clk",

				"gtbu_clk";

		qcom,retention;

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&gfx_iommu 0>;

			qcom,gpu-offset = <0xa000>;

		};

	};

};

#include "qcs405-ion.dtsi"

#include "qcs405-pm.dtsi"

#include "msm-arm-smmu-qcs405.dtsi"

#include "qcs405-gpu.dtsi"

&soc {

	#address-cells = <1>;