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Commit c7b66698 authored by Stefan Roese's avatar Stefan Roese Committed by Josh Boyer
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powerpc/40x: Add support for PPC40x boards with > 512MB SDRAM 



This patch adds support for boards with more that 512MByte RAM. Currently
only 512MB of memory are enabled in the DCCR/ICCR real-mode cache
control registers. This patch now enables caching in real-mode for
2GByte.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
parent 573bff5a

arch/powerpc/mm/40x_mmu.c

+2 −2
Original line number Diff line number Diff line
@@ -84,8 +84,8 @@ void __init MMU_init_hw(void) 
	 * vectors and the kernel live in real-mode.

	 */



        mtspr(SPRN_DCCR, 0xF0000000);	/* 512 MB of data space at 0x0. */

        mtspr(SPRN_ICCR, 0xF0000000);	/* 512 MB of instr. space at 0x0. */

        mtspr(SPRN_DCCR, 0xFFFF0000);	/* 2GByte of data space at 0x0. */

        mtspr(SPRN_ICCR, 0xFFFF0000);	/* 2GByte of instr. space at 0x0. */

}



#define LARGE_PAGE_SIZE_16M	(1<<24)