Merge "drivers: clk: qcom: update dsi pll as per latest recommendations" (c71a7452) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/fb/mdss-pll.txt

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -19,7 +19,8 @@ Required properties:
	"qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",		"qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",
	"qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm",		"qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm",
	"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm",		"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm",
	"qcom,mdss_dp_pll_14nm", "qcom,mdss_hdmi_pll_28lpm"		"qcom,mdss_dp_pll_14nm", "qcom,mdss_hdmi_pll_28lpm",
			"qcom,mdss_dsi_pll_7nm_v2"
	- cell-index: Specifies the controller used		- cell-index: Specifies the controller used
	- reg: offset and length of the register set for the device.		- reg: offset and length of the register set for the device.
	- reg-names : names to refer to register sets related to this device		- reg-names : names to refer to register sets related to this device

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -52,6 +52,14 @@
	/delete-property/ qcom,smmu-s1-bypass;		/delete-property/ qcom,smmu-s1-bypass;
	};		};

			&mdss_dsi0_pll {
			compatible = "qcom,mdss_dsi_pll_7nm_v2";
			};

			&mdss_dsi1_pll {
			compatible = "qcom,mdss_dsi_pll_7nm_v2";
			};

	&spss_utils {		&spss_utils {
	qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */		qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
	qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */		qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+34 −4

Original line number	Original line	Diff line number	Diff line
	@@ -250,6 +250,18 @@ struct dsi_pll_7nm {
	struct dsi_pll_regs reg_setup;		struct dsi_pll_regs reg_setup;
	};		};

			static inline bool dsi_pll_7nm_is_hw_revision_v1(
			struct mdss_pll_resources *rsc)
			{
			return (rsc->pll_interface_type == MDSS_DSI_PLL_7NM) ? true : false;
			}

			static inline bool dsi_pll_7nm_is_hw_revision_v2(
			struct mdss_pll_resources *rsc)
			{
			return (rsc->pll_interface_type == MDSS_DSI_PLL_7NM_V2) ? true : false;
			}

	static inline int pll_reg_read(void *context, unsigned int reg,		static inline int pll_reg_read(void *context, unsigned int reg,
	unsigned int *val)		unsigned int *val)
	{		{
	@@ -519,7 +531,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll,

	dec = div_u64(dec_multiple, multiplier);		dec = div_u64(dec_multiple, multiplier);

	regs->pll_clock_inverters = 0;		if (dsi_pll_7nm_is_hw_revision_v1(rsc))
			regs->pll_clock_inverters = 0x0;
			else
			regs->pll_clock_inverters = 0x28;

	regs->pll_lockdet_rate = config->lock_timer;		regs->pll_lockdet_rate = config->lock_timer;
	regs->decimal_div_start = dec;		regs->decimal_div_start = dec;
	regs->frac_div_start_low = (frac & 0xff);		regs->frac_div_start_low = (frac & 0xff);
	@@ -605,7 +621,12 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll,

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x01);		MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
	MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);		MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);

			if (dsi_pll_7nm_is_hw_revision_v1(rsc))
	MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x21);		MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x21);
			else
			MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x22);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE, 0x01);		MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE, 0x01);
	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03);		MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03);
	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00);		MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00);
	@@ -626,7 +647,11 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll,
	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29);		MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29);
	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x2f);		MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x2f);
	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x2a);		MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x2a);
	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3f);
			if (dsi_pll_7nm_is_hw_revision_v1(rsc))
			MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x30);
			else
			MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x22);
	}		}

	static void dsi_pll_init_val(struct mdss_pll_resources *rsc)		static void dsi_pll_init_val(struct mdss_pll_resources *rsc)
	@@ -717,7 +742,12 @@ static void dsi_pll_init_val(struct mdss_pll_resources *rsc)
	MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_MIN_DELAY, 0x00000019);		MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_MIN_DELAY, 0x00000019);
	MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, 0x00000000);		MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, 0x00000000);
	MDSS_PLL_REG_W(pll_base, PLL_SPARE_AND_JPC_OVERRIDES, 0x00000000);		MDSS_PLL_REG_W(pll_base, PLL_SPARE_AND_JPC_OVERRIDES, 0x00000000);

			if (dsi_pll_7nm_is_hw_revision_v1(rsc))
			MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x00000066);
			else
	MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x00000040);		MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x00000040);

	MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_2, 0x00000020);		MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_2, 0x00000020);
	MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x00000000);		MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x00000000);
	MDSS_PLL_REG_W(pll_base, PLL_COMMON_STATUS_ONE, 0x00000000);		MDSS_PLL_REG_W(pll_base, PLL_COMMON_STATUS_ONE, 0x00000000);

drivers/clk/qcom/mdss/mdss-pll.c

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -134,6 +134,8 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
	pll_res->pll_interface_type = MDSS_DP_PLL_7NM;		pll_res->pll_interface_type = MDSS_DP_PLL_7NM;
	else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm"))		else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm"))
	pll_res->pll_interface_type = MDSS_DSI_PLL_7NM;		pll_res->pll_interface_type = MDSS_DSI_PLL_7NM;
			else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_7nm_v2"))
			pll_res->pll_interface_type = MDSS_DSI_PLL_7NM_V2;
	else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_28lpm"))		else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_28lpm"))
	pll_res->pll_interface_type = MDSS_DSI_PLL_28LPM;		pll_res->pll_interface_type = MDSS_DSI_PLL_28LPM;
	else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_14nm"))		else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_14nm"))
	@@ -171,6 +173,7 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
	rc = dp_pll_clock_register_10nm(pdev, pll_res);		rc = dp_pll_clock_register_10nm(pdev, pll_res);
	break;		break;
	case MDSS_DSI_PLL_7NM:		case MDSS_DSI_PLL_7NM:
			case MDSS_DSI_PLL_7NM_V2:
	rc = dsi_pll_clock_register_7nm(pdev, pll_res);		rc = dsi_pll_clock_register_7nm(pdev, pll_res);
	break;		break;
	case MDSS_DP_PLL_7NM:		case MDSS_DP_PLL_7NM:
	@@ -417,6 +420,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
	{.compatible = "qcom,mdss_dsi_pll_10nm"},		{.compatible = "qcom,mdss_dsi_pll_10nm"},
	{.compatible = "qcom,mdss_dp_pll_10nm"},		{.compatible = "qcom,mdss_dp_pll_10nm"},
	{.compatible = "qcom,mdss_dsi_pll_7nm"},		{.compatible = "qcom,mdss_dsi_pll_7nm"},
			{.compatible = "qcom,mdss_dsi_pll_7nm_v2"},
	{.compatible = "qcom,mdss_dp_pll_7nm"},		{.compatible = "qcom,mdss_dp_pll_7nm"},
	{.compatible = "qcom,mdss_dsi_pll_28lpm"},		{.compatible = "qcom,mdss_dsi_pll_28lpm"},
	{.compatible = "qcom,mdss_dsi_pll_14nm"},		{.compatible = "qcom,mdss_dsi_pll_14nm"},

drivers/clk/qcom/mdss/mdss-pll.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -44,6 +44,7 @@ enum {
	MDSS_DSI_PLL_10NM,		MDSS_DSI_PLL_10NM,
	MDSS_DP_PLL_10NM,		MDSS_DP_PLL_10NM,
	MDSS_DSI_PLL_7NM,		MDSS_DSI_PLL_7NM,
			MDSS_DSI_PLL_7NM_V2,
	MDSS_DP_PLL_7NM,		MDSS_DP_PLL_7NM,
	MDSS_DSI_PLL_28LPM,		MDSS_DSI_PLL_28LPM,
	MDSS_DSI_PLL_14NM,		MDSS_DSI_PLL_14NM,