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Commit c6946274 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gcc: Remove the throttle clocks for TRINKET"

parents ff43a75f aaf56d07

drivers/clk/qcom/gcc-trinket.c

+0 −46
Original line number Diff line number Diff line
@@ -2868,34 +2868,6 @@ static struct clk_branch gcc_cpuss_gnoc_clk = { 
	},

};



static struct clk_branch gcc_cpuss_throttle_core_clk = {

	.halt_reg = 0x2b180,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x2b180,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x79004,

		.enable_mask = BIT(30),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_throttle_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_cpuss_throttle_xo_clk = {

	.halt_reg = 0x2b17c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2b17c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_throttle_xo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_disp_ahb_clk = {

	.halt_reg = 0x1700c,

	.halt_check = BRANCH_HALT,
@@ -3231,21 +3203,6 @@ static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 
	},

};



static struct clk_branch gcc_qmip_cpuss_cfg_ahb_clk = {

	.halt_reg = 0x2b178,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x2b178,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x79004,

		.enable_mask = BIT(18),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qmip_cpuss_cfg_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qmip_disp_ahb_clk = {

	.halt_reg = 0x17018,

	.halt_check = BRANCH_HALT,
@@ -4270,8 +4227,6 @@ static struct clk_regmap *gcc_trinket_clocks[] = { 
	[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,

	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,

	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,

	[GCC_CPUSS_THROTTLE_CORE_CLK] = &gcc_cpuss_throttle_core_clk.clkr,

	[GCC_CPUSS_THROTTLE_XO_CLK] = &gcc_cpuss_throttle_xo_clk.clkr,

	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,

	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,

	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
@@ -4298,7 +4253,6 @@ static struct clk_regmap *gcc_trinket_clocks[] = { 
	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,

	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,

	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,

	[GCC_QMIP_CPUSS_CFG_AHB_CLK] = &gcc_qmip_cpuss_cfg_ahb_clk.clkr,

	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,

	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,

	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,

include/dt-bindings/clock/qcom,gcc-trinket.h

+107 −110
Original line number Diff line number Diff line
@@ -119,116 +119,113 @@ 
#define GCC_CE1_CLK				102

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK		103

#define GCC_CPUSS_GNOC_CLK			104

#define GCC_CPUSS_THROTTLE_CORE_CLK		105

#define GCC_CPUSS_THROTTLE_XO_CLK		106

#define GCC_DISP_AHB_CLK			107

#define GCC_DISP_GPLL0_DIV_CLK_SRC		108

#define GCC_DISP_HF_AXI_CLK			109

#define GCC_DISP_THROTTLE_CORE_CLK		110

#define GCC_DISP_XO_CLK				111

#define GCC_GP1_CLK				112

#define GCC_GP1_CLK_SRC				113

#define GCC_GP2_CLK				114

#define GCC_GP2_CLK_SRC				115

#define GCC_GP3_CLK				116

#define GCC_GP3_CLK_SRC				117

#define GCC_GPU_CFG_AHB_CLK			118

#define GCC_GPU_GPLL0_CLK_SRC			119

#define GCC_GPU_GPLL0_DIV_CLK_SRC		120

#define GCC_GPU_MEMNOC_GFX_CLK			121

#define GCC_GPU_SNOC_DVM_GFX_CLK		122

#define GCC_GPU_THROTTLE_CORE_CLK		123

#define GCC_GPU_THROTTLE_XO_CLK			124

#define GCC_MSS_VS_CLK				125

#define GCC_PDM2_CLK				126

#define GCC_PDM2_CLK_SRC			127

#define GCC_PDM_AHB_CLK				128

#define GCC_PDM_XO4_CLK				129

#define GCC_PRNG_AHB_CLK			130

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		131

#define GCC_QMIP_CAMERA_RT_AHB_CLK		132

#define GCC_QMIP_CPUSS_CFG_AHB_CLK		133

#define GCC_QMIP_DISP_AHB_CLK			134

#define GCC_QMIP_GPU_CFG_AHB_CLK		135

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		136

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		137

#define GCC_QUPV3_WRAP0_CORE_CLK		138

#define GCC_QUPV3_WRAP0_S0_CLK			139

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		140

#define GCC_QUPV3_WRAP0_S1_CLK			141

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		142

#define GCC_QUPV3_WRAP0_S2_CLK			143

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		144

#define GCC_QUPV3_WRAP0_S3_CLK			145

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		146

#define GCC_QUPV3_WRAP0_S4_CLK			147

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		148

#define GCC_QUPV3_WRAP0_S5_CLK			149

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		150

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		151

#define GCC_QUPV3_WRAP1_CORE_CLK		152

#define GCC_QUPV3_WRAP1_S0_CLK			153

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		154

#define GCC_QUPV3_WRAP1_S1_CLK			155

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		156

#define GCC_QUPV3_WRAP1_S2_CLK			157

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		158

#define GCC_QUPV3_WRAP1_S3_CLK			159

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		160

#define GCC_QUPV3_WRAP1_S4_CLK			161

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		162

#define GCC_QUPV3_WRAP1_S5_CLK			163

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		164

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		165

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		166

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		167

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		168

#define GCC_SDCC1_AHB_CLK			169

#define GCC_SDCC1_APPS_CLK			170

#define GCC_SDCC1_APPS_CLK_SRC			171

#define GCC_SDCC1_ICE_CORE_CLK			172

#define GCC_SDCC1_ICE_CORE_CLK_SRC		173

#define GCC_SDCC2_AHB_CLK			174

#define GCC_SDCC2_APPS_CLK			175

#define GCC_SDCC2_APPS_CLK_SRC			176

#define GCC_SYS_NOC_CPUSS_AHB_CLK		177

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		178

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		179

#define GCC_UFS_PHY_AHB_CLK			180

#define GCC_UFS_PHY_AXI_CLK			181

#define GCC_UFS_PHY_AXI_CLK_SRC			182

#define GCC_UFS_PHY_ICE_CORE_CLK		183

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		184

#define GCC_UFS_PHY_PHY_AUX_CLK			185

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		186

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		187

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		188

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		189

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		190

#define GCC_USB30_PRIM_MASTER_CLK		191

#define GCC_USB30_PRIM_MASTER_CLK_SRC		192

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		193

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	194

#define GCC_USB30_PRIM_SLEEP_CLK		195

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		196

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		197

#define GCC_USB3_PRIM_PHY_PIPE_CLK		198

#define GCC_VDDA_VS_CLK				199

#define GCC_VDDCX_VS_CLK			200

#define GCC_VDDMX_VS_CLK			201

#define GCC_VIDEO_AHB_CLK			202

#define GCC_VIDEO_AXI0_CLK			203

#define GCC_VIDEO_THROTTLE_CORE_CLK		204

#define GCC_VIDEO_XO_CLK			205

#define GCC_VS_CTRL_AHB_CLK			206

#define GCC_VS_CTRL_CLK				207

#define GCC_VS_CTRL_CLK_SRC			208

#define GCC_VSENSOR_CLK_SRC			209

#define GCC_WCSS_VS_CLK				210

#define GCC_USB3_PRIM_CLKREF_CLK		211

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		212

#define GCC_BIMC_GPU_AXI_CLK			213

#define GCC_UFS_MEM_CLKREF_CLK			214

#define GCC_DISP_AHB_CLK			105

#define GCC_DISP_GPLL0_DIV_CLK_SRC		106

#define GCC_DISP_HF_AXI_CLK			107

#define GCC_DISP_THROTTLE_CORE_CLK		108

#define GCC_DISP_XO_CLK				109

#define GCC_GP1_CLK				110

#define GCC_GP1_CLK_SRC				111

#define GCC_GP2_CLK				112

#define GCC_GP2_CLK_SRC				113

#define GCC_GP3_CLK				114

#define GCC_GP3_CLK_SRC				115

#define GCC_GPU_CFG_AHB_CLK			116

#define GCC_GPU_GPLL0_CLK_SRC			117

#define GCC_GPU_GPLL0_DIV_CLK_SRC		118

#define GCC_GPU_MEMNOC_GFX_CLK			119

#define GCC_GPU_SNOC_DVM_GFX_CLK		120

#define GCC_GPU_THROTTLE_CORE_CLK		121

#define GCC_GPU_THROTTLE_XO_CLK			122

#define GCC_MSS_VS_CLK				123

#define GCC_PDM2_CLK				124

#define GCC_PDM2_CLK_SRC			125

#define GCC_PDM_AHB_CLK				126

#define GCC_PDM_XO4_CLK				127

#define GCC_PRNG_AHB_CLK			128

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		129

#define GCC_QMIP_CAMERA_RT_AHB_CLK		130

#define GCC_QMIP_DISP_AHB_CLK			131

#define GCC_QMIP_GPU_CFG_AHB_CLK		132

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		133

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		134

#define GCC_QUPV3_WRAP0_CORE_CLK		135

#define GCC_QUPV3_WRAP0_S0_CLK			136

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		137

#define GCC_QUPV3_WRAP0_S1_CLK			138

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		139

#define GCC_QUPV3_WRAP0_S2_CLK			140

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		141

#define GCC_QUPV3_WRAP0_S3_CLK			142

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		143

#define GCC_QUPV3_WRAP0_S4_CLK			144

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		145

#define GCC_QUPV3_WRAP0_S5_CLK			146

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		147

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		148

#define GCC_QUPV3_WRAP1_CORE_CLK		149

#define GCC_QUPV3_WRAP1_S0_CLK			150

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		151

#define GCC_QUPV3_WRAP1_S1_CLK			152

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		153

#define GCC_QUPV3_WRAP1_S2_CLK			154

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		155

#define GCC_QUPV3_WRAP1_S3_CLK			156

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		157

#define GCC_QUPV3_WRAP1_S4_CLK			158

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		159

#define GCC_QUPV3_WRAP1_S5_CLK			160

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		161

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		162

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		163

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		164

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		165

#define GCC_SDCC1_AHB_CLK			166

#define GCC_SDCC1_APPS_CLK			167

#define GCC_SDCC1_APPS_CLK_SRC			168

#define GCC_SDCC1_ICE_CORE_CLK			169

#define GCC_SDCC1_ICE_CORE_CLK_SRC		170

#define GCC_SDCC2_AHB_CLK			171

#define GCC_SDCC2_APPS_CLK			172

#define GCC_SDCC2_APPS_CLK_SRC			173

#define GCC_SYS_NOC_CPUSS_AHB_CLK		174

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		175

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		176

#define GCC_UFS_PHY_AHB_CLK			177

#define GCC_UFS_PHY_AXI_CLK			178

#define GCC_UFS_PHY_AXI_CLK_SRC			179

#define GCC_UFS_PHY_ICE_CORE_CLK		180

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		181

#define GCC_UFS_PHY_PHY_AUX_CLK			182

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		183

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		184

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		185

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		186

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		187

#define GCC_USB30_PRIM_MASTER_CLK		188

#define GCC_USB30_PRIM_MASTER_CLK_SRC		189

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		190

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	191

#define GCC_USB30_PRIM_SLEEP_CLK		192

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		193

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		194

#define GCC_USB3_PRIM_PHY_PIPE_CLK		195

#define GCC_VDDA_VS_CLK				196

#define GCC_VDDCX_VS_CLK			197

#define GCC_VDDMX_VS_CLK			198

#define GCC_VIDEO_AHB_CLK			199

#define GCC_VIDEO_AXI0_CLK			200

#define GCC_VIDEO_THROTTLE_CORE_CLK		201

#define GCC_VIDEO_XO_CLK			202

#define GCC_VS_CTRL_AHB_CLK			203

#define GCC_VS_CTRL_CLK				204

#define GCC_VS_CTRL_CLK_SRC			205

#define GCC_VSENSOR_CLK_SRC			206

#define GCC_WCSS_VS_CLK				207

#define GCC_USB3_PRIM_CLKREF_CLK		208

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		209

#define GCC_BIMC_GPU_AXI_CLK			210

#define GCC_UFS_MEM_CLKREF_CLK			211



/* GCC Resets */

#define GCC_QUSB2PHY_PRIM_BCR			0