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Commit c596704f authored by Padmavathi Venna's avatar Padmavathi Venna Committed by Kukjin Kim
Browse files

ARM: S5P64X0: Add SPI clkdev support 



Registered the SPI bus clocks with clkdev using generic
connection id.

Signed-off-by: default avatarPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 02717bb9

arch/arm/mach-s5p64x0/clock-s5p6440.c

+29 −32
Original line number Original line Diff line number Diff line
@@ -267,18 +267,6 @@ static struct clk init_clocks_off[] = { 
		.parent		= &clk_pclk.clk,

		.parent		= &clk_pclk.clk,

		.enable		= s5p64x0_pclk_ctrl,

		.enable		= s5p64x0_pclk_ctrl,

		.ctrlbit	= (1 << 31),

		.ctrlbit	= (1 << 31),

	}, {

		.name		= "sclk_spi_48",

		.devname	= "s3c64xx-spi.0",

		.parent		= &clk_48m,

		.enable		= s5p64x0_sclk_ctrl,

		.ctrlbit	= (1 << 22),

	}, {

		.name		= "sclk_spi_48",

		.devname	= "s3c64xx-spi.1",

		.parent		= &clk_48m,

		.enable		= s5p64x0_sclk_ctrl,

		.ctrlbit	= (1 << 23),

	}, {

	}, {

		.name		= "mmc_48m",

		.name		= "mmc_48m",

		.devname	= "s3c-sdhci.0",

		.devname	= "s3c-sdhci.0",
@@ -419,26 +407,6 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &clkset_group1,

		.sources = &clkset_group1,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },

		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.0",

			.ctrlbit	= (1 << 20),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group1,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.1",

			.ctrlbit	= (1 << 21),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group1,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

	}, {

	}, {

		.clk	= {

		.clk	= {

			.name		= "sclk_post",

			.name		= "sclk_post",
@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = { 
	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },

};

};





static struct clksrc_clk clk_sclk_spi0 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.0",

		.ctrlbit	= (1 << 20),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group1,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi1 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.1",

		.ctrlbit	= (1 << 21),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group1,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

};



/* Clock initialization code */

/* Clock initialization code */

static struct clksrc_clk *sysclks[] = {

static struct clksrc_clk *sysclks[] = {

	&clk_mout_apll,

	&clk_mout_apll,
@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = { 




static struct clksrc_clk *clksrc_cdev[] = {

static struct clksrc_clk *clksrc_cdev[] = {

	&clk_sclk_uclk,

	&clk_sclk_uclk,

	&clk_sclk_spi0,

	&clk_sclk_spi1,

};

};





static struct clk_lookup s5p6440_clk_lookup[] = {

static struct clk_lookup s5p6440_clk_lookup[] = {

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),

	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),

};

};





void __init_or_cpufreq s5p6440_setup_clocks(void)

void __init_or_cpufreq s5p6440_setup_clocks(void)

arch/arm/mach-s5p64x0/clock-s5p6450.c

+29 −20
Original line number Original line Diff line number Diff line
@@ -441,26 +441,6 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &clkset_group2,

		.sources = &clkset_group2,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },

		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.0",

			.ctrlbit	= (1 << 20),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group2,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.1",

			.ctrlbit	= (1 << 21),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group2,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

	}, {

	}, {

		.clk	= {

		.clk	= {

			.name		= "sclk_fimc",

			.name		= "sclk_fimc",
@@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = { 
	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },

};

};





static struct clksrc_clk clk_sclk_spi0 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.0",

		.ctrlbit	= (1 << 20),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group2,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi1 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.1",

		.ctrlbit	= (1 << 21),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group2,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

};



static struct clksrc_clk *clksrc_cdev[] = {

static struct clksrc_clk *clksrc_cdev[] = {

	&clk_sclk_uclk,

	&clk_sclk_uclk,

	&clk_sclk_spi0,

	&clk_sclk_spi1,

};

};





static struct clk_lookup s5p6450_clk_lookup[] = {

static struct clk_lookup s5p6450_clk_lookup[] = {

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),

	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),

};

};





/* Clock initialization code */

/* Clock initialization code */